2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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2023-10-24 12:59:35 +02:00
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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2023-08-30 17:31:07 +02:00
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title: MediaTek Infrastructure System Configuration Controller
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maintainers:
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- Matthias Brugger <matthias.bgg@gmail.com>
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description:
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The Mediatek infracfg controller provides various clocks and reset outputs
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to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
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and reset values in <dt-bindings/reset/mt*-reset.h> and
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<dt-bindings/reset/mt*-resets.h>.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- mediatek,mt2701-infracfg
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- mediatek,mt2712-infracfg
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- mediatek,mt6765-infracfg
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- mediatek,mt6795-infracfg
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- mediatek,mt6779-infracfg_ao
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- mediatek,mt6797-infracfg
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- mediatek,mt7622-infracfg
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- mediatek,mt7629-infracfg
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- mediatek,mt7981-infracfg
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- mediatek,mt7986-infracfg
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- mediatek,mt8135-infracfg
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- mediatek,mt8167-infracfg
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- mediatek,mt8173-infracfg
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- mediatek,mt8183-infracfg
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- mediatek,mt8516-infracfg
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- const: syscon
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- items:
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- const: mediatek,mt7623-infracfg
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- const: mediatek,mt2701-infracfg
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt2701-infracfg
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- mediatek,mt2712-infracfg
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- mediatek,mt6795-infracfg
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- mediatek,mt7622-infracfg
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- mediatek,mt7986-infracfg
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- mediatek,mt8135-infracfg
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- mediatek,mt8173-infracfg
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- mediatek,mt8183-infracfg
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then:
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required:
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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infracfg: clock-controller@10001000 {
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compatible = "mediatek,mt8173-infracfg", "syscon";
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reg = <0x10001000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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