54 lines
1.0 KiB
YAML
54 lines
1.0 KiB
YAML
|
# SPDX-License-Identifier: GPL-2.0
|
||
|
|
%YAML 1.2
|
||
|
|
---
|
||
|
|
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml#
|
||
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||
|
|
|
||
|
|
title: Allwinner A10 Peripheral PLL
|
||
|
|
|
||
|
|
maintainers:
|
||
|
|
- Chen-Yu Tsai <wens@csie.org>
|
||
|
|
- Maxime Ripard <mripard@kernel.org>
|
||
|
|
|
||
|
|
deprecated: true
|
||
|
|
|
||
|
|
properties:
|
||
|
|
"#clock-cells":
|
||
|
|
const: 1
|
||
|
|
description: >
|
||
|
|
The first output is the SATA clock output, the second is the
|
||
|
|
regular PLL output, the third is a PLL output at twice the rate.
|
||
|
|
|
||
|
|
compatible:
|
||
|
|
const: allwinner,sun4i-a10-pll6-clk
|
||
|
|
|
||
|
|
reg:
|
||
|
|
maxItems: 1
|
||
|
|
|
||
|
|
clocks:
|
||
|
|
maxItems: 1
|
||
|
|
|
||
|
|
clock-output-names:
|
||
|
|
maxItems: 3
|
||
|
|
|
||
|
|
required:
|
||
|
|
- "#clock-cells"
|
||
|
|
- compatible
|
||
|
|
- reg
|
||
|
|
- clocks
|
||
|
|
- clock-output-names
|
||
|
|
|
||
|
|
additionalProperties: false
|
||
|
|
|
||
|
|
examples:
|
||
|
|
- |
|
||
|
|
clk@1c20028 {
|
||
|
|
#clock-cells = <1>;
|
||
|
|
compatible = "allwinner,sun4i-a10-pll6-clk";
|
||
|
|
reg = <0x01c20028 0x4>;
|
||
|
|
clocks = <&osc24M>;
|
||
|
|
clock-output-names = "pll6_sata", "pll6_other", "pll6";
|
||
|
|
};
|
||
|
|
|
||
|
|
...
|