66 lines
2.1 KiB
YAML
66 lines
2.1 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on SDX75
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maintainers:
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- Imran Shaik <quic_imrashai@quicinc.com>
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on SDX75
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See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h
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properties:
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compatible:
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const: qcom,sdx75-gcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: EMAC0 sgmiiphy mac rclk source
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- description: EMAC0 sgmiiphy mac tclk source
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- description: EMAC0 sgmiiphy rclk source
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- description: EMAC0 sgmiiphy tclk source
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- description: EMAC1 sgmiiphy mac rclk source
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- description: EMAC1 sgmiiphy mac tclk source
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- description: EMAC1 sgmiiphy rclk source
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- description: EMAC1 sgmiiphy tclk source
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- description: PCIE20 phy aux clock source
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- description: PCIE_1 Pipe clock source
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- description: PCIE_2 Pipe clock source
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- description: PCIE Pipe clock source
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- description: USB3 phy wrapper pipe clock source
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required:
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- compatible
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- clocks
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@80000 {
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compatible = "qcom,sdx75-gcc";
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reg = <0x80000 0x1f7400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>,
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<&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>,
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<&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>,
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<&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>,
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<&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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