69 lines
1.6 KiB
YAML
69 lines
1.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM8350 Video Clock & Reset Controller
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maintainers:
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- Konrad Dybcio <konrad.dybcio@linaro.org>
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description: |
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Qualcomm video clock control module provides the clocks, resets and power
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domains on Qualcomm SoCs.
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See also::
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include/dt-bindings/clock/qcom,videocc-sm8350.h
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include/dt-bindings/reset/qcom,videocc-sm8350.h
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properties:
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compatible:
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const: qcom,sm8350-videocc
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Board sleep clock
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power-domains:
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description:
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A phandle and PM domain specifier for the MMCX power domain.
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maxItems: 1
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required-opps:
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description:
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A phandle to an OPP node describing required MMCX performance point.
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maxItems: 1
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required:
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- compatible
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- clocks
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- power-domains
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- required-opps
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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clock-controller@abf0000 {
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compatible = "qcom,sm8350-videocc";
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reg = <0x0abf0000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&sleep_clk>;
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power-domains = <&rpmhpd SM8350_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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