91 lines
3.6 KiB
YAML
91 lines
3.6 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/lvds.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: LVDS Display Common Properties
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maintainers:
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- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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- Thierry Reding <thierry.reding@gmail.com>
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description: |+
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LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
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incompatible data link layers have been used over time to transmit image data
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to LVDS devices. This bindings supports devices compatible with the following
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specifications.
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[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
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1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
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[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
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Semiconductor
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[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
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Electronics Standards Association (VESA)
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Device compatible with those specifications have been marketed under the
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FPD-Link and FlatLink brands.
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properties:
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data-mapping:
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enum:
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- jeida-18
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- jeida-24
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- vesa-24
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description: |
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The color signals mapping order.
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LVDS data mappings are defined as follows.
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- "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
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[VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
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Slot 0 1 2 3 4 5 6
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________________ _________________
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Clock \_______________________/
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______ ______ ______ ______ ______ ______ ______
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DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
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DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
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DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
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- "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
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specifications. Data are transferred as follows on 4 LVDS lanes.
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Slot 0 1 2 3 4 5 6
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________________ _________________
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Clock \_______________________/
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______ ______ ______ ______ ______ ______ ______
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DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
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DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
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DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
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DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
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- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
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Data are transferred as follows on 4 LVDS lanes.
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Slot 0 1 2 3 4 5 6
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________________ _________________
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Clock \_______________________/
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______ ______ ______ ______ ______ ______ ______
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DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
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DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
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DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
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DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
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Control signals are mapped as follows.
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CTL0: HSync
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CTL1: VSync
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CTL2: Data Enable
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CTL3: 0
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data-mirror:
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type: boolean
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description:
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If set, reverse the bit order described in the data mappings below on all
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data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.
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additionalProperties: true
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...
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