95 lines
2.8 KiB
Plaintext
95 lines
2.8 KiB
Plaintext
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Rockchip specific extensions to the Synopsys Designware MIPI DSI
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================================
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Required properties:
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- #address-cells: Should be <1>.
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- #size-cells: Should be <0>.
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- compatible: one of
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"rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
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"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
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"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
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"rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"
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- reg: Represent the physical address range of the controller.
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- interrupts: Represent the controller's interrupt to the CPU(s).
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- clocks, clock-names: Phandles to the controller's pll reference
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clock(ref) when using an internal dphy and APB clock(pclk).
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For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
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are required. As described in [1].
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- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
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- ports: contain a port node with endpoint definitions as defined in [2].
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For vopb,set the reg = <0> and set the reg = <1> for vopl.
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- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
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- video port 1 for either a panel or subsequent encoder
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Optional properties:
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- phys: from general PHY binding: the phandle for the PHY device.
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- phy-names: Should be "dphy" if phys references an external phy.
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- #phy-cells: Defined when used as ISP phy, should be 0.
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- power-domains: a phandle to mipi dsi power domain node.
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- resets: list of phandle + reset specifier pairs, as described in [3].
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- reset-names: string reset name, must be "apb".
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/media/video-interfaces.txt
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[3] Documentation/devicetree/bindings/reset/reset.txt
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Example:
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mipi_dsi: mipi@ff960000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
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reg = <0xff960000 0x4000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
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clock-names = "ref", "pclk";
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resets = <&cru SRST_MIPIDSI0>;
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reset-names = "apb";
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rockchip,grf = <&grf>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_vopb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_mipi>;
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};
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mipi_in_vopl: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_mipi>;
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};
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};
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mipi_out: port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_out_panel: endpoint {
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remote-endpoint = <&panel_in_mipi>;
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};
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};
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};
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panel {
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compatible ="boe,tv080wum-nl0";
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reg = <0>;
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enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_en>;
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backlight = <&backlight>;
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port {
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panel_in_mipi: endpoint {
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remote-endpoint = <&mipi_out_panel>;
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};
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};
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};
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};
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