2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Zynq FPGA Manager
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maintainers:
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2023-10-24 12:59:35 +02:00
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- Michal Simek <michal.simek@amd.com>
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2023-08-30 17:31:07 +02:00
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properties:
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compatible:
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const: xlnx,zynq-devcfg-1.0
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: ref_clk
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syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to syscon block which provide access to SLCR registers
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- syscon
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additionalProperties: false
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examples:
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- |
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devcfg: devcfg@f8007000 {
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compatible = "xlnx,zynq-devcfg-1.0";
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reg = <0xf8007000 0x100>;
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interrupts = <0 8 4>;
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clocks = <&clkc 12>;
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clock-names = "ref_clk";
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syscon = <&slcr>;
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};
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