2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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2023-10-24 12:59:35 +02:00
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$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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2023-08-30 17:31:07 +02:00
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title: NVIDIA Tegra NVDEC
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description: |
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NVDEC is the hardware video decoder present on NVIDIA Tegra210
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and newer chips. It is located on the Host1x bus and typically
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programmed through Host1x channels.
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maintainers:
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- Thierry Reding <treding@gmail.com>
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- Mikko Perttunen <mperttunen@nvidia.com>
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properties:
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$nodename:
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pattern: "^nvdec@[0-9a-f]*$"
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compatible:
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enum:
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- nvidia,tegra210-nvdec
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- nvidia,tegra186-nvdec
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- nvidia,tegra194-nvdec
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: nvdec
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: nvdec
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power-domains:
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maxItems: 1
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iommus:
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maxItems: 1
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dma-coherent: true
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interconnects:
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items:
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- description: DMA read memory client
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- description: DMA read 2 memory client
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- description: DMA write memory client
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interconnect-names:
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items:
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- const: dma-mem
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- const: read-1
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- const: write
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nvidia,host1x-class:
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description: |
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Host1x class of the engine, used to specify the targeted engine
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when programming the engine through Host1x channels or when
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configuring engine-specific behavior in Host1x.
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default: 0xf0
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$ref: /schemas/types.yaml#/definitions/uint32
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra186-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/memory/tegra186-mc.h>
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#include <dt-bindings/power/tegra186-powergate.h>
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#include <dt-bindings/reset/tegra186-reset.h>
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nvdec@15480000 {
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compatible = "nvidia,tegra186-nvdec";
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reg = <0x15480000 0x40000>;
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clocks = <&bpmp TEGRA186_CLK_NVDEC>;
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clock-names = "nvdec";
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resets = <&bpmp TEGRA186_RESET_NVDEC>;
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reset-names = "nvdec";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
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interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
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<&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
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<&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
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interconnect-names = "dma-mem", "read-1", "write";
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iommus = <&smmu TEGRA186_SID_NVDEC>;
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};
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