174 lines
4.4 KiB
YAML
174 lines
4.4 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: i.MX8 Image Sensing Interface
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maintainers:
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- Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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description: |
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The Image Sensing Interface (ISI) combines image processing pipelines with
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DMA engines to process and capture frames originating from a variety of
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sources. The inputs to the ISI go through Pixel Link interfaces, and their
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number and nature is SoC-dependent. They cover both capture interfaces (MIPI
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CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
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properties:
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compatible:
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enum:
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- fsl,imx8mn-isi
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- fsl,imx8mp-isi
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reg:
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maxItems: 1
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clocks:
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items:
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- description: The AXI clock
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- description: The APB clock
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# TODO: Check if the per-channel ipg_proc_clk clocks need to be specified
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# as well, in case some SoCs have the ability to control them separately.
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# This may be the case of the i.MX8[DQ]X(P)
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clock-names:
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items:
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- const: axi
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- const: apb
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fsl,blk-ctrl:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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A phandle referencing the block control that contains the CSIS to ISI
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gasket.
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interrupts:
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description: Processing pipeline interrupts, one per pipeline
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minItems: 1
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maxItems: 2
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power-domains:
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description: |
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Ports represent the Pixel Link inputs to the ISI. Their number and
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assignment are model-dependent. Each port shall have a single endpoint.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- fsl,blk-ctrl
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- ports
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx8mn-isi
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then:
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properties:
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interrupts:
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maxItems: 1
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ports:
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properties:
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port@0:
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description: MIPI CSI-2 RX
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required:
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- port@0
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx8mp-isi
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then:
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properties:
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interrupts:
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maxItems: 2
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ports:
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properties:
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port@0:
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description: MIPI CSI-2 RX 0
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port@1:
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description: MIPI CSI-2 RX 1
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required:
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- port@0
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- port@1
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mn-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/imx8mn-power.h>
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isi@32e20000 {
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compatible = "fsl,imx8mn-isi";
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reg = <0x32e20000 0x100>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
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<&clk IMX8MN_CLK_DISP_APB_ROOT>;
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clock-names = "axi", "apb";
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fsl,blk-ctrl = <&disp_blk_ctrl>;
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power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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isi_in: endpoint {
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remote-endpoint = <&mipi_csi_out>;
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};
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};
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};
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};
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- |
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#include <dt-bindings/clock/imx8mp-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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isi@32e00000 {
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compatible = "fsl,imx8mp-isi";
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reg = <0x32e00000 0x4000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
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clock-names = "axi", "apb";
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fsl,blk-ctrl = <&media_blk_ctrl>;
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power-domains = <&mediamix_pd>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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isi_in_0: endpoint {
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remote-endpoint = <&mipi_csi_0_out>;
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};
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};
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port@1 {
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reg = <1>;
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isi_in_1: endpoint {
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remote-endpoint = <&mipi_csi_1_out>;
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};
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};
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};
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};
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...
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