85 lines
2.1 KiB
YAML
85 lines
2.1 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0+
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/adi,adin.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices ADIN1200/ADIN1300 PHY
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maintainers:
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- Alexandru Tachici <alexandru.tachici@analog.com>
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description: |
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Bindings for Analog Devices Industrial Ethernet PHYs
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allOf:
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- $ref: ethernet-phy.yaml#
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properties:
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adi,rx-internal-delay-ps:
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description: |
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RGMII RX Clock Delay used only when PHY operates in RGMII mode with
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internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
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enum: [ 1600, 1800, 2000, 2200, 2400 ]
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default: 2000
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adi,tx-internal-delay-ps:
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description: |
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RGMII TX Clock Delay used only when PHY operates in RGMII mode with
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internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
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enum: [ 1600, 1800, 2000, 2200, 2400 ]
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default: 2000
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adi,fifo-depth-bits:
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description: |
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When operating in RMII mode, this option configures the FIFO depth.
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enum: [ 4, 8, 12, 16, 20, 24 ]
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default: 8
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adi,phy-output-clock:
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description: |
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Select clock output on GP_CLK pin. Two clocks are available:
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A 25MHz reference and a free-running 125MHz.
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The phy can alternatively automatically switch between the reference and
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the 125MHz clocks based on its internal state.
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$ref: /schemas/types.yaml#/definitions/string
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enum:
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- 25mhz-reference
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- 125mhz-free-running
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- adaptive-free-running
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adi,phy-output-reference-clock:
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description: Enable 25MHz reference clock output on CLK25_REF pin.
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type: boolean
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unevaluatedProperties: false
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examples:
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- |
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ethernet {
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#address-cells = <1>;
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#size-cells = <0>;
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phy-mode = "rgmii-id";
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ethernet-phy@0 {
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reg = <0>;
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adi,rx-internal-delay-ps = <1800>;
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adi,tx-internal-delay-ps = <2200>;
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};
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};
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- |
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ethernet {
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#address-cells = <1>;
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#size-cells = <0>;
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phy-mode = "rmii";
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ethernet-phy@1 {
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reg = <1>;
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adi,fifo-depth-bits = <16>;
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};
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};
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