2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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2023-10-24 12:59:35 +02:00
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$id: http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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2023-08-30 17:31:07 +02:00
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title: Intel Keem Bay PCIe controller Endpoint mode
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maintainers:
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- Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
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- Srikanth Thokala <srikanth.thokala@intel.com>
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properties:
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compatible:
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const: intel,keembay-pcie-ep
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reg:
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maxItems: 5
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: atu
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- const: addr_space
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- const: apb
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interrupts:
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maxItems: 4
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interrupt-names:
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items:
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- const: pcie
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- const: pcie_ev
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- const: pcie_err
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- const: pcie_mem_access
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num-lanes:
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description: Number of lanes to use.
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enum: [ 1, 2 ]
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pcie-ep@37000000 {
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compatible = "intel,keembay-pcie-ep";
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reg = <0x37000000 0x00001000>,
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<0x37100000 0x00001000>,
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<0x37300000 0x00001000>,
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<0x36000000 0x01000000>,
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<0x37800000 0x00000200>;
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reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
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num-lanes = <2>;
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};
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