89 lines
2.0 KiB
YAML
89 lines
2.0 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx AXI PCIe Root Port Bridge
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maintainers:
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- Thippeswamy Havalige <thippeswamy.havalige@amd.com>
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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properties:
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compatible:
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const: xlnx,axi-pcie-host-1.00.a
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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ranges:
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items:
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- description: |
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ranges for the PCI memory regions (I/O space region is not
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supported by hardware)
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"#interrupt-cells":
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const: 1
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interrupt-controller:
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description: identifies the node as an interrupt controller
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type: object
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properties:
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interrupt-controller: true
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"#address-cells":
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const: 0
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"#interrupt-cells":
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const: 1
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required:
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- interrupt-controller
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- "#address-cells"
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- "#interrupt-cells"
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additionalProperties: false
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required:
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- compatible
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- reg
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- ranges
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- interrupts
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- interrupt-map
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- "#interrupt-cells"
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- interrupt-controller
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pcie@50000000 {
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compatible = "xlnx,axi-pcie-host-1.00.a";
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reg = <0x50000000 0x1000000>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 1>,
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<0 0 0 2 &pcie_intc 2>,
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<0 0 0 3 &pcie_intc 3>,
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<0 0 0 4 &pcie_intc 4>;
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ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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