83 lines
2.0 KiB
YAML
83 lines
2.0 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: HiSilicon Kirin970 PCIe PHY
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maintainers:
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- Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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description: |+
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Bindings for PCIe PHY on HiSilicon Kirin 970.
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properties:
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compatible:
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const: hisilicon,hi970-pcie-phy
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"#phy-cells":
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const: 0
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reg:
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maxItems: 1
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description: PHY Control registers
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phy-supply:
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description: The PCIe PHY power supply
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clocks:
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items:
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- description: PCIe PHY clock
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- description: PCIe AUX clock
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- description: PCIe APB PHY clock
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- description: PCIe APB SYS clock
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- description: PCIe ACLK clock
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clock-names:
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items:
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- const: phy_ref
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- const: aux
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- const: apb_phy
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- const: apb_sys
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- const: aclk
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hisilicon,eye-diagram-param:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: Eye diagram for phy.
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required:
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- "#phy-cells"
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- compatible
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- reg
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- clocks
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- clock-names
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- hisilicon,eye-diagram-param
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- phy-supply
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/hi3670-clock.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie_phy: pcie-phy@fc000000 {
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compatible = "hisilicon,hi970-pcie-phy";
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reg = <0x0 0xfc000000 0x0 0x80000>;
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#phy-cells = <0>;
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phy-supply = <&ldo33>;
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clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
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<&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
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<&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
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<&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
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<&crg_ctrl HI3670_ACLK_GATE_PCIE>;
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clock-names = "phy_ref", "aux",
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"apb_phy", "apb_sys", "aclk";
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hisilicon,eye-diagram-param = <0xffffffff 0xffffffff
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0xffffffff 0xffffffff 0xffffffff>;
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};
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};
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