101 lines
2.4 KiB
YAML
101 lines
2.4 KiB
YAML
|
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||
|
|
%YAML 1.2
|
||
|
|
---
|
||
|
|
$id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
|
||
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||
|
|
|
||
|
|
title: Microchip Sparx5 Serdes controller
|
||
|
|
|
||
|
|
maintainers:
|
||
|
|
- Steen Hegelund <steen.hegelund@microchip.com>
|
||
|
|
|
||
|
|
description: |
|
||
|
|
The Sparx5 SERDES interfaces share the same basic functionality, but
|
||
|
|
support different operating modes and line rates.
|
||
|
|
|
||
|
|
The following list lists the SERDES features:
|
||
|
|
|
||
|
|
* RX Adaptive Decision Feedback Equalizer (DFE)
|
||
|
|
* Programmable continuous time linear equalizer (CTLE)
|
||
|
|
* Rx variable gain control
|
||
|
|
* Rx built-in fault detector (loss-of-lock/loss-of-signal)
|
||
|
|
* Adjustable tx de-emphasis (FFE)
|
||
|
|
* Tx output amplitude control
|
||
|
|
* Supports rx eye monitor
|
||
|
|
* Multiple loopback modes
|
||
|
|
* Prbs generator and checker
|
||
|
|
* Polarity inversion control
|
||
|
|
|
||
|
|
SERDES6G:
|
||
|
|
|
||
|
|
The SERDES6G is a high-speed SERDES interface, which can operate at
|
||
|
|
the following data rates:
|
||
|
|
|
||
|
|
* 100 Mbps (100BASE-FX)
|
||
|
|
* 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
|
||
|
|
* 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
|
||
|
|
* 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
|
||
|
|
|
||
|
|
SERDES10G
|
||
|
|
|
||
|
|
The SERDES10G is a high-speed SERDES interface, which can operate at
|
||
|
|
the following data rates:
|
||
|
|
|
||
|
|
* 100 Mbps (100BASE-FX)
|
||
|
|
* 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
|
||
|
|
* 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
|
||
|
|
* 5 Gbps (QSGMII/USGMII)
|
||
|
|
* 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
|
||
|
|
* 10 Gbps (10G-USGMII)
|
||
|
|
* 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
|
||
|
|
|
||
|
|
SERDES25G
|
||
|
|
|
||
|
|
The SERDES25G is a high-speed SERDES interface, which can operate at
|
||
|
|
the following data rates:
|
||
|
|
|
||
|
|
* 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
|
||
|
|
* 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
|
||
|
|
* 5 Gbps (QSGMII/USGMII)
|
||
|
|
* 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
|
||
|
|
* 10 Gbps (10G-USGMII)
|
||
|
|
* 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
|
||
|
|
* 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)
|
||
|
|
|
||
|
|
properties:
|
||
|
|
$nodename:
|
||
|
|
pattern: "^serdes@[0-9a-f]+$"
|
||
|
|
|
||
|
|
compatible:
|
||
|
|
const: microchip,sparx5-serdes
|
||
|
|
|
||
|
|
reg:
|
||
|
|
minItems: 1
|
||
|
|
|
||
|
|
'#phy-cells':
|
||
|
|
const: 1
|
||
|
|
description: |
|
||
|
|
- The main serdes input port
|
||
|
|
|
||
|
|
clocks:
|
||
|
|
maxItems: 1
|
||
|
|
|
||
|
|
required:
|
||
|
|
- compatible
|
||
|
|
- reg
|
||
|
|
- '#phy-cells'
|
||
|
|
- clocks
|
||
|
|
|
||
|
|
additionalProperties: false
|
||
|
|
|
||
|
|
examples:
|
||
|
|
- |
|
||
|
|
serdes: serdes@10808000 {
|
||
|
|
compatible = "microchip,sparx5-serdes";
|
||
|
|
#phy-cells = <1>;
|
||
|
|
clocks = <&sys_clk>;
|
||
|
|
reg = <0x10808000 0x5d0000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
...
|