60 lines
2.0 KiB
Plaintext
60 lines
2.0 KiB
Plaintext
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HiSilicon STB PCIE/SATA/USB3 PHY
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Required properties:
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- compatible: Should be "hisilicon,hi3798cv200-combphy"
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- reg: Should be the address space for COMBPHY configuration and state
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registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and
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PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC.
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- #phy-cells: Should be 1. The cell number is used to select the phy mode
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as defined in <dt-bindings/phy/phy.h>.
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- clocks: The phandle to clock provider and clock specifier pair.
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- resets: The phandle to reset controller and reset specifier pair.
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Refer to phy/phy-bindings.txt for the generic PHY binding properties.
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Optional properties:
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- hisilicon,fixed-mode: If the phy device doesn't support mode select
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but a fixed mode setting, the property should be present to specify
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the particular mode.
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- hisilicon,mode-select-bits: If the phy device support mode select,
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this property should be present to specify the register bits in
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peripheral controller, as a 3 integers tuple:
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<register_offset bit_shift bit_mask>.
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Notes:
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- Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only
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one of them should be present.
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- The device node should be a child of peripheral controller that contains
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COMBPHY configuration/state and PERI_CTRL register used to select PHY mode.
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Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller
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bindings.
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Examples:
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perictrl: peripheral-controller@8a20000 {
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compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
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"simple-mfd";
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reg = <0x8a20000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x8a20000 0x1000>;
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combphy0: phy@850 {
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compatible = "hisilicon,hi3798cv200-combphy";
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reg = <0x850 0x8>;
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#phy-cells = <1>;
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clocks = <&crg HISTB_COMBPHY0_CLK>;
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resets = <&crg 0x188 4>;
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hisilicon,fixed-mode = <PHY_TYPE_USB3>;
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};
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combphy1: phy@858 {
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compatible = "hisilicon,hi3798cv200-combphy";
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reg = <0x858 0x8>;
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#phy-cells = <1>;
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clocks = <&crg HISTB_COMBPHY1_CLK>;
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resets = <&crg 0x188 12>;
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hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
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};
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};
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