2023-08-30 17:31:07 +02:00
|
|
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
|
|
|
%YAML 1.2
|
|
|
|
---
|
|
|
|
$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-ufs-phy.yaml#
|
|
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
|
|
|
|
title: Qualcomm QMP PHY controller (UFS, MSM8996)
|
|
|
|
|
|
|
|
maintainers:
|
|
|
|
- Vinod Koul <vkoul@kernel.org>
|
|
|
|
|
|
|
|
description:
|
|
|
|
QMP PHY controller supports physical layer functionality for a number of
|
|
|
|
controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
|
|
|
|
|
|
|
|
Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
|
|
|
|
qcom,sc8280xp-qmp-ufs-phy.yaml.
|
|
|
|
|
|
|
|
properties:
|
|
|
|
compatible:
|
|
|
|
enum:
|
|
|
|
- qcom,msm8996-qmp-ufs-phy
|
|
|
|
- qcom,msm8998-qmp-ufs-phy
|
|
|
|
- qcom,sc8180x-qmp-ufs-phy
|
|
|
|
- qcom,sdm845-qmp-ufs-phy
|
|
|
|
- qcom,sm6115-qmp-ufs-phy
|
|
|
|
- qcom,sm6350-qmp-ufs-phy
|
|
|
|
- qcom,sm8150-qmp-ufs-phy
|
|
|
|
- qcom,sm8250-qmp-ufs-phy
|
|
|
|
- qcom,sm8350-qmp-ufs-phy
|
|
|
|
- qcom,sm8450-qmp-ufs-phy
|
|
|
|
|
|
|
|
reg:
|
|
|
|
items:
|
|
|
|
- description: serdes
|
|
|
|
|
|
|
|
"#address-cells":
|
|
|
|
enum: [ 1, 2 ]
|
|
|
|
|
|
|
|
"#size-cells":
|
|
|
|
enum: [ 1, 2 ]
|
|
|
|
|
|
|
|
ranges: true
|
|
|
|
|
|
|
|
clocks:
|
|
|
|
minItems: 1
|
|
|
|
maxItems: 3
|
|
|
|
|
|
|
|
clock-names:
|
|
|
|
minItems: 1
|
|
|
|
maxItems: 3
|
|
|
|
|
|
|
|
power-domains:
|
|
|
|
maxItems: 1
|
|
|
|
|
|
|
|
resets:
|
|
|
|
maxItems: 1
|
|
|
|
|
|
|
|
reset-names:
|
|
|
|
items:
|
|
|
|
- const: ufsphy
|
|
|
|
|
|
|
|
vdda-phy-supply: true
|
|
|
|
|
|
|
|
vdda-pll-supply: true
|
|
|
|
|
|
|
|
vddp-ref-clk-supply: true
|
|
|
|
|
|
|
|
patternProperties:
|
|
|
|
"^phy@[0-9a-f]+$":
|
|
|
|
type: object
|
|
|
|
description: single PHY-provider child node
|
|
|
|
properties:
|
|
|
|
reg:
|
|
|
|
minItems: 3
|
|
|
|
maxItems: 6
|
|
|
|
|
|
|
|
"#clock-cells":
|
|
|
|
const: 1
|
|
|
|
|
|
|
|
"#phy-cells":
|
|
|
|
const: 0
|
|
|
|
|
|
|
|
required:
|
|
|
|
- reg
|
|
|
|
- "#phy-cells"
|
|
|
|
|
|
|
|
additionalProperties: false
|
|
|
|
|
|
|
|
required:
|
|
|
|
- compatible
|
|
|
|
- reg
|
|
|
|
- "#address-cells"
|
|
|
|
- "#size-cells"
|
|
|
|
- ranges
|
|
|
|
- clocks
|
|
|
|
- clock-names
|
|
|
|
- resets
|
|
|
|
- reset-names
|
|
|
|
- vdda-phy-supply
|
|
|
|
- vdda-pll-supply
|
|
|
|
|
|
|
|
additionalProperties: false
|
|
|
|
|
|
|
|
allOf:
|
|
|
|
- if:
|
|
|
|
properties:
|
|
|
|
compatible:
|
|
|
|
contains:
|
|
|
|
enum:
|
|
|
|
- qcom,msm8996-qmp-ufs-phy
|
|
|
|
then:
|
|
|
|
properties:
|
|
|
|
clocks:
|
|
|
|
maxItems: 1
|
|
|
|
clock-names:
|
|
|
|
items:
|
|
|
|
- const: ref
|
|
|
|
|
|
|
|
- if:
|
|
|
|
properties:
|
|
|
|
compatible:
|
|
|
|
contains:
|
|
|
|
enum:
|
|
|
|
- qcom,msm8998-qmp-ufs-phy
|
|
|
|
- qcom,sc8180x-qmp-ufs-phy
|
|
|
|
- qcom,sdm845-qmp-ufs-phy
|
|
|
|
- qcom,sm6115-qmp-ufs-phy
|
|
|
|
- qcom,sm6350-qmp-ufs-phy
|
|
|
|
- qcom,sm8150-qmp-ufs-phy
|
|
|
|
- qcom,sm8250-qmp-ufs-phy
|
|
|
|
then:
|
|
|
|
properties:
|
|
|
|
clocks:
|
|
|
|
maxItems: 2
|
|
|
|
clock-names:
|
|
|
|
items:
|
|
|
|
- const: ref
|
|
|
|
- const: ref_aux
|
|
|
|
|
|
|
|
- if:
|
|
|
|
properties:
|
|
|
|
compatible:
|
|
|
|
contains:
|
|
|
|
enum:
|
|
|
|
- qcom,sm8450-qmp-ufs-phy
|
|
|
|
then:
|
|
|
|
properties:
|
|
|
|
clocks:
|
|
|
|
maxItems: 3
|
|
|
|
clock-names:
|
|
|
|
items:
|
|
|
|
- const: ref
|
|
|
|
- const: ref_aux
|
|
|
|
- const: qref
|
|
|
|
|
|
|
|
- if:
|
|
|
|
properties:
|
|
|
|
compatible:
|
|
|
|
contains:
|
|
|
|
enum:
|
|
|
|
- qcom,msm8998-qmp-ufs-phy
|
2023-10-24 12:59:35 +02:00
|
|
|
- qcom,sc8180x-qmp-ufs-phy
|
2023-08-30 17:31:07 +02:00
|
|
|
- qcom,sdm845-qmp-ufs-phy
|
|
|
|
- qcom,sm6350-qmp-ufs-phy
|
|
|
|
- qcom,sm8150-qmp-ufs-phy
|
|
|
|
- qcom,sm8250-qmp-ufs-phy
|
|
|
|
- qcom,sm8350-qmp-ufs-phy
|
|
|
|
- qcom,sm8450-qmp-ufs-phy
|
|
|
|
then:
|
|
|
|
patternProperties:
|
|
|
|
"^phy@[0-9a-f]+$":
|
|
|
|
properties:
|
|
|
|
reg:
|
|
|
|
items:
|
|
|
|
- description: TX lane 1
|
|
|
|
- description: RX lane 1
|
|
|
|
- description: PCS
|
|
|
|
- description: TX lane 2
|
|
|
|
- description: RX lane 2
|
|
|
|
|
|
|
|
- if:
|
|
|
|
properties:
|
|
|
|
compatible:
|
|
|
|
contains:
|
|
|
|
enum:
|
|
|
|
- qcom,msm8996-qmp-ufs-phy
|
|
|
|
- qcom,sm6115-qmp-ufs-phy
|
|
|
|
then:
|
|
|
|
patternProperties:
|
|
|
|
"^phy@[0-9a-f]+$":
|
|
|
|
properties:
|
|
|
|
reg:
|
|
|
|
items:
|
|
|
|
- description: TX
|
|
|
|
- description: RX
|
|
|
|
- description: PCS
|
|
|
|
|
|
|
|
examples:
|
|
|
|
- |
|
|
|
|
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
|
|
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
|
|
|
|
|
|
|
phy-wrapper@1d87000 {
|
|
|
|
compatible = "qcom,sm8250-qmp-ufs-phy";
|
|
|
|
reg = <0x01d87000 0x1c0>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0x0 0x01d87000 0x1000>;
|
|
|
|
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
|
|
|
|
clock-names = "ref", "ref_aux";
|
|
|
|
|
|
|
|
resets = <&ufs_mem_hc 0>;
|
|
|
|
reset-names = "ufsphy";
|
|
|
|
|
|
|
|
vdda-phy-supply = <&vreg_l6b>;
|
|
|
|
vdda-pll-supply = <&vreg_l3b>;
|
|
|
|
|
|
|
|
phy@400 {
|
|
|
|
reg = <0x400 0x108>,
|
|
|
|
<0x600 0x1e0>,
|
|
|
|
<0xc00 0x1dc>,
|
|
|
|
<0x800 0x108>,
|
|
|
|
<0xa00 0x1e0>;
|
|
|
|
#phy-cells = <0>;
|
|
|
|
};
|
|
|
|
};
|