229 lines
7.1 KiB
YAML
229 lines
7.1 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek MT6795 Pin Controller
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maintainers:
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- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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- Sean Wang <sean.wang@kernel.org>
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description:
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The MediaTek's MT6795 Pin controller is used to control SoC pins.
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properties:
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compatible:
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const: mediatek,mt6795-pinctrl
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gpio-controller: true
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'#gpio-cells':
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description:
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Number of cells in GPIO specifier. Since the generic GPIO binding is used,
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the amount of cells must be specified as 2. See the below mentioned gpio
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binding representation for description of particular cells.
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const: 2
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gpio-ranges:
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description: GPIO valid number range.
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maxItems: 1
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reg:
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description:
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Physical address base for GPIO base and eint registers.
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minItems: 2
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reg-names:
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items:
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- const: base
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- const: eint
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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interrupts:
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description: Interrupt outputs to the system interrupt controller (sysirq).
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minItems: 1
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items:
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- description: EINT interrupt
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- description: EINT event_b interrupt
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# PIN CONFIGURATION NODES
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patternProperties:
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'-pins$':
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type: object
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additionalProperties: false
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patternProperties:
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'^pins':
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type: object
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additionalProperties: false
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description: |
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A pinctrl node should contain at least one subnodes representing the
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pinctrl groups available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to muxer
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configuration, pullups, drive strength, input enable/disable and input
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schmitt.
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An example of using macro:
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pincontroller {
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/* GPIO0 set as multifunction GPIO0 */
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gpio-pins {
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pins {
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pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
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}
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};
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/* GPIO45 set as multifunction SDA0 */
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i2c0-pins {
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pins {
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pinmux = <PINMUX_GPIO45__FUNC_SDA0>;
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}
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};
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};
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$ref: pinmux-node.yaml
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properties:
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pinmux:
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description:
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Integer array, represents gpio pin number and mux setting.
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Supported pin number and mux varies for different SoCs, and are
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defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
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drive-strength:
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enum: [2, 4, 6, 8, 10, 12, 14, 16]
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bias-pull-down:
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oneOf:
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- type: boolean
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- enum: [100, 101, 102, 103]
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description: mt6795 pull down PUPD/R0/R1 type define value.
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description:
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For normal pull down type, it is not necessary to specify R1R0
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values; When pull down type is PUPD/R0/R1, adding R1R0 defines
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will set different resistance values.
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bias-pull-up:
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oneOf:
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- type: boolean
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- enum: [100, 101, 102, 103]
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description: mt6795 pull up PUPD/R0/R1 type define value.
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description:
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For normal pull up type, it is not necessary to specify R1R0
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values; When pull up type is PUPD/R0/R1, adding R1R0 defines will
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set different resistance values.
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bias-disable: true
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output-high: true
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output-low: true
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input-enable: true
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input-disable: true
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input-schmitt-enable: true
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input-schmitt-disable: true
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mediatek,pull-up-adv:
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description: |
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Pull up setings for 2 pull resistors, R0 and R1. User can
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configure those special pins. Valid arguments are described as
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below:
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0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
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1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
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2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
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3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3]
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mediatek,pull-down-adv:
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description: |
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Pull down settings for 2 pull resistors, R0 and R1. User can
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configure those special pins. Valid arguments are described as
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below:
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0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
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1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
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2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
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3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3]
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required:
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- pinmux
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allOf:
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- $ref: pinctrl.yaml#
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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- gpio-controller
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- '#gpio-cells'
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- gpio-ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt6795-pinctrl";
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reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
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reg-names = "base", "eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 196>;
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interrupt-controller;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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i2c0-pins {
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pins-sda-scl {
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pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
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<PINMUX_GPIO46__FUNC_SCL0>;
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};
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};
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mmc0-pins {
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pins-cmd-dat {
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pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
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<PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
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<PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
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<PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
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<PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
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<PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
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<PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
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<PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
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<PINMUX_GPIO162__FUNC_MSDC0_CMD>;
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input-enable;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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pins-clk {
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pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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};
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pins-rst {
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pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
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};
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};
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};
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};
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