154 lines
4.4 KiB
YAML
154 lines
4.4 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sm7150-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM7150 TLMM pin controller
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Danila Tikhonov <danila@jiaxyga.com>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SM7150 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,sm7150-tlmm
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: west
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- const: north
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- const: south
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 60
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gpio-line-names:
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maxItems: 119
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sm7150-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sm7150-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sm7150-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
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- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
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sdc2_cmd, sdc2_data, ufs_reset ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ gpio, adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
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atest_tsens2, atest_usb1, atest_usb2, cam_mclk, cci_async,
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cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
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cci_timer4, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2,
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ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0,
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gp_pdm1, gp_pdm2, gps_tx, jitter_bist, ldo_en, ldo_update,
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m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
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mdp_vsync3, mss_lte, nav_pps_in, nav_pps_out, pa_indicator,
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pci_e, phase_flag, pll_bist, pll_bypassnl, pll_reset, pri_mi2s,
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pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
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qlink_request, qua_mi2s, qup00, qup01, qup02, qup03, qup04,
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qup10, qup11, qup12, qup13, qup14, qup15, sd_write, sdc40,
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sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, ter_mi2s,
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tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsif1_clk, tsif1_data,
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tsif1_en, tsif1_error, tsif1_sync, tsif2_clk, tsif2_data,
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tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data,
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uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
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uim2_reset, uim_batt, usb_phy, vfr_1, vsense_trigger,
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wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk,
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wsa_data ]
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required:
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- pins
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required:
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- compatible
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- reg
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- reg-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@3500000 {
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compatible = "qcom,sm7150-tlmm";
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reg = <0x03500000 0x300000>,
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<0x03900000 0x300000>,
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<0x03d00000 0x300000>;
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reg-names = "west", "north", "south";
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&tlmm 0 0 120>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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wakeup-parent = <&pdc>;
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gpio-wo-state {
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pins = "gpio1";
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function = "gpio";
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};
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uart-w-state {
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rx-pins {
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pins = "gpio44";
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function = "qup12";
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bias-pull-up;
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};
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tx-pins {
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pins = "gpio45";
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function = "qup12";
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bias-disable;
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};
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};
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};
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...
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