121 lines
3.2 KiB
YAML
121 lines
3.2 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/fsl,spdif.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
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maintainers:
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- Shengjiu Wang <shengjiu.wang@nxp.com>
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description: |
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The Freescale S/PDIF audio block is a stereo transceiver that allows the
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processor to receive and transmit digital audio via an coaxial cable or
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a fibre cable.
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properties:
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compatible:
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enum:
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- fsl,imx35-spdif
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- fsl,vf610-spdif
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- fsl,imx6sx-spdif
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- fsl,imx8qm-spdif
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- fsl,imx8qxp-spdif
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- fsl,imx8mq-spdif
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- fsl,imx8mm-spdif
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- fsl,imx8mn-spdif
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- fsl,imx8ulp-spdif
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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dmas:
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items:
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- description: DMA controller phandle and request line for RX
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- description: DMA controller phandle and request line for TX
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dma-names:
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items:
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- const: rx
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- const: tx
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clocks:
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items:
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- description: The core clock of spdif controller.
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- description: Clock for tx0 and rx0.
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- description: Clock for tx1 and rx1.
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- description: Clock for tx2 and rx2.
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- description: Clock for tx3 and rx3.
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- description: Clock for tx4 and rx4.
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- description: Clock for tx5 and rx5.
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- description: Clock for tx6 and rx6.
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- description: Clock for tx7 and rx7.
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- description: The spba clock is required when SPDIF is placed as a bus
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slave of the Shared Peripheral Bus and when two or more bus masters
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(CPU, DMA or DSP) try to access it. This property is optional depending
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on the SoC design.
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- description: PLL clock source for 8kHz series rate, optional.
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- description: PLL clock source for 11khz series rate, optional.
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minItems: 9
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clock-names:
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items:
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- const: core
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- const: rxtx0
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- const: rxtx1
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- const: rxtx2
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- const: rxtx3
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- const: rxtx4
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- const: rxtx5
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- const: rxtx6
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- const: rxtx7
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- const: spba
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- const: pll8k
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- const: pll11k
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minItems: 9
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big-endian:
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$ref: /schemas/types.yaml#/definitions/flag
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description: |
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If this property is absent, the native endian mode will be in use
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as default, or the big endian mode will be in use for all the device
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registers. Set this flag for HCDs with big endian descriptors and big
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endian registers.
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required:
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- compatible
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- reg
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- interrupts
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- dmas
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- dma-names
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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spdif@2004000 {
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compatible = "fsl,imx35-spdif";
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reg = <0x02004000 0x4000>;
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interrupts = <0 52 0x04>;
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dmas = <&sdma 14 18 0>,
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<&sdma 15 18 0>;
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dma-names = "rx", "tx";
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clocks = <&clks 197>, <&clks 3>,
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<&clks 197>, <&clks 107>,
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<&clks 0>, <&clks 118>,
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<&clks 62>, <&clks 139>,
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<&clks 0>;
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clock-names = "core", "rxtx0",
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"rxtx1", "rxtx2",
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"rxtx3", "rxtx4",
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"rxtx5", "rxtx6",
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"rxtx7";
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big-endian;
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};
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