2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Quad Serial Peripheral Interface (QSPI)
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: The QSPI controller allows SPI protocol communication in single,
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dual, or quad wire transmission modes for read/write access to slaves such
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as NOR flash.
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allOf:
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- $ref: /schemas/spi/spi-controller.yaml#
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properties:
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compatible:
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items:
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- enum:
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- qcom,sc7180-qspi
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- qcom,sc7280-qspi
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- qcom,sdm845-qspi
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- const: qcom,qspi-v1
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reg:
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maxItems: 1
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2023-10-24 12:59:35 +02:00
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iommus:
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maxItems: 1
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2023-08-30 17:31:07 +02:00
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interrupts:
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maxItems: 1
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clock-names:
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items:
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- const: iface
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- const: core
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clocks:
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items:
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- description: AHB clock
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- description: QSPI core clock
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interconnects:
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minItems: 1
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maxItems: 2
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interconnect-names:
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minItems: 1
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items:
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- const: qspi-config
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- const: qspi-memory
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operating-points-v2: true
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clock-names
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc: soc {
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#address-cells = <2>;
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#size-cells = <2>;
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qspi: spi@88df000 {
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compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
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reg = <0 0x88df000 0 0x600>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "iface", "core";
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clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
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<&gcc GCC_QSPI_CORE_CLK>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <25000000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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};
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};
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};
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...
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