239 lines
8.9 KiB
Plaintext
239 lines
8.9 KiB
Plaintext
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Tegra124 SOCTHERM thermal management system
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The SOCTHERM IP block contains thermal sensors, support for polled
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or interrupt-based thermal monitoring, CPU and GPU throttling based
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on temperature trip points, and handling external overcurrent
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notifications. It is also used to manage emergency shutdown in an
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overheating situation.
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Required properties :
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- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
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For Tegra132, must contain "nvidia,tegra132-soctherm".
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For Tegra210, must contain "nvidia,tegra210-soctherm".
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- reg : Should contain at least 2 entries for each entry in reg-names:
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- SOCTHERM register set
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- Tegra CAR register set: Required for Tegra124 and Tegra210.
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- CCROC register set: Required for Tegra132.
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- reg-names : Should contain at least 2 entries:
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- soctherm-reg
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- car-reg
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- ccroc-reg
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- interrupts : Defines the interrupt used by SOCTHERM
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names : Must include the following entries:
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- tsensor
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- soctherm
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Must include the following entries:
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- soctherm
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- #thermal-sensor-cells : Should be 1. For a description of this property, see
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Documentation/devicetree/bindings/thermal/thermal-sensor.yaml.
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See <dt-bindings/thermal/tegra124-soctherm.h> for a list of valid values
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when referring to thermal sensors.
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- throttle-cfgs: A sub-node which is a container of configuration for each
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hardware throttle events. These events can be set as cooling devices.
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* throttle events: Sub-nodes must be named as "light" or "heavy".
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Properties:
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- nvidia,priority: Each throttles has its own throttle settings, so the
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SW need to set priorities for various throttle, the HW arbiter can select
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the final throttle settings.
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Bigger value indicates higher priority, In general, higher priority
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translates to lower target frequency. SW needs to ensure that critical
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thermal alarms are given higher priority, and ensure that there is
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no race if priority of two vectors is set to the same value.
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The range of this value is 1~100.
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- nvidia,cpu-throt-percent: This property is for Tegra124 and Tegra210.
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It is the throttling depth of pulse skippers, it's the percentage
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throttling.
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- nvidia,cpu-throt-level: This property is only for Tegra132, it is the
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level of pulse skippers, which used to throttle clock frequencies. It
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indicates cpu clock throttling depth, and the depth can be programmed.
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Must set as following values:
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TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED
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TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE
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- nvidia,gpu-throt-level: This property is for Tegra124 and Tegra210.
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It is the level of pulse skippers, which used to throttle clock
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frequencies. It indicates gpu clock throttling depth and can be
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programmed to any of the following values which represent a throttling
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percentage:
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TEGRA_SOCTHERM_THROT_LEVEL_NONE (0%)
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TEGRA_SOCTHERM_THROT_LEVEL_LOW (50%),
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TEGRA_SOCTHERM_THROT_LEVEL_MED (75%),
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TEGRA_SOCTHERM_THROT_LEVEL_HIGH (85%).
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- #cooling-cells: Should be 1. This cooling device only support on/off state.
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For a description of this property see:
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Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
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Optional properties: The following properties are T210 specific and
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valid only for OCx throttle events.
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- nvidia,count-threshold: Specifies the number of OC events that are
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required for triggering an interrupt. Interrupts are not triggered if
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the property is missing. A value of 0 will interrupt on every OC alarm.
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- nvidia,polarity-active-low: Configures the polarity of the OC alaram
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signal. If present, this means assert low, otherwise assert high.
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- nvidia,alarm-filter: Number of clocks to filter event. When the filter
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expires (which means the OC event has not occurred for a long time),
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the counter is cleared and filter is rearmed. Default value is 0.
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- nvidia,throttle-period-us: Specifies the number of uSec for which
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throttling is engaged after the OC event is deasserted. Default value
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is 0.
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Optional properties:
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- nvidia,thermtrips : When present, this property specifies the temperature at
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which the soctherm hardware will assert the thermal trigger signal to the
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Power Management IC, which can be configured to reset or shutdown the device.
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It is an array of pairs where each pair represents a tsensor id followed by a
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temperature in milli Celcius. In the absence of this property the critical
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trip point will be used for thermtrip temperature.
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Note:
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- the "critical" type trip points will be used to set the temperature at which
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the SOC_THERM hardware will assert a thermal trigger if the "nvidia,thermtrips"
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property is missing. When the thermtrips property is present, the breach of a
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critical trip point is reported back to the thermal framework to implement
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software shutdown.
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- the "hot" type trip points will be set to SOC_THERM hardware as the throttle
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temperature. Once the temperature of this thermal zone is higher
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than it, it will trigger the HW throttle event.
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Example :
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soctherm@700e2000 {
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compatible = "nvidia,tegra124-soctherm";
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reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
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0x0 0x60006000 0x0 0x400 /* CAR reg_base */
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reg-names = "soctherm-reg", "car-reg";
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
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<&tegra_car TEGRA124_CLK_SOC_THERM>;
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clock-names = "tsensor", "soctherm";
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resets = <&tegra_car 78>;
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reset-names = "soctherm";
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#thermal-sensor-cells = <1>;
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nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500
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TEGRA124_SOCTHERM_SENSOR_GPU 103000>;
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throttle-cfgs {
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/*
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* When the "heavy" cooling device triggered,
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* the HW will skip cpu clock's pulse in 85% depth,
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* skip gpu clock's pulse in 85% level
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*/
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throttle_heavy: heavy {
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nvidia,priority = <100>;
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nvidia,cpu-throt-percent = <85>;
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nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
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#cooling-cells = <1>;
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};
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/*
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* When the "light" cooling device triggered,
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* the HW will skip cpu clock's pulse in 50% depth,
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* skip gpu clock's pulse in 50% level
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*/
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throttle_light: light {
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nvidia,priority = <80>;
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nvidia,cpu-throt-percent = <50>;
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nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>;
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#cooling-cells = <1>;
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};
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/*
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* If these two devices are triggered in same time, the HW throttle
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* arbiter will select the highest priority as the final throttle
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* settings to skip cpu pulse.
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*/
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throttle_oc1: oc1 {
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nvidia,priority = <50>;
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nvidia,polarity-active-low;
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nvidia,count-threshold = <100>;
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nvidia,alarm-filter = <5100000>;
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nvidia,throttle-period-us = <0>;
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nvidia,cpu-throt-percent = <75>;
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nvidia,gpu-throt-level =
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<TEGRA_SOCTHERM_THROT_LEVEL_MED>;
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};
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};
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};
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Example: referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" :
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soctherm@700e2000 {
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compatible = "nvidia,tegra132-soctherm";
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reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
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0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
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reg-names = "soctherm-reg", "ccroc-reg";
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throttle-cfgs {
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/*
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* When the "heavy" cooling device triggered,
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* the HW will skip cpu clock's pulse in HIGH level
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*/
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throttle_heavy: heavy {
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nvidia,priority = <100>;
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nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
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#cooling-cells = <1>;
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};
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/*
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* When the "light" cooling device triggered,
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* the HW will skip cpu clock's pulse in MED level
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*/
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throttle_light: light {
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nvidia,priority = <80>;
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nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
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#cooling-cells = <1>;
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};
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/*
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* If these two devices are triggered in same time, the HW throttle
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* arbiter will select the highest priority as the final throttle
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* settings to skip cpu pulse.
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*/
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};
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};
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Example: referring to thermal sensors :
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thermal-zones {
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cpu {
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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thermal-sensors =
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<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
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trips {
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cpu_shutdown_trip: shutdown-trip {
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temperature = <102500>;
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hysteresis = <1000>;
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type = "critical";
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};
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cpu_throttle_trip: throttle-trip {
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temperature = <100000>;
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hysteresis = <1000>;
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type = "hot";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_throttle_trip>;
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cooling-device = <&throttle_heavy 1 1>;
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};
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};
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};
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};
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