2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung SoC series UFS host controller
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maintainers:
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- Alim Akhtar <alim.akhtar@samsung.com>
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description: |
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Each Samsung UFS host controller instance should have its own node.
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allOf:
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- $ref: ufs-common.yaml
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properties:
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compatible:
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enum:
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- samsung,exynos7-ufs
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- samsung,exynosautov9-ufs
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- samsung,exynosautov9-ufs-vh
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- tesla,fsd-ufs
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reg:
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items:
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- description: HCI register
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- description: vendor specific register
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- description: unipro register
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- description: UFS protector register
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reg-names:
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items:
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- const: hci
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- const: vs_hci
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- const: unipro
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- const: ufsp
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clocks:
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items:
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- description: ufs link core clock
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- description: unipro main clock
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clock-names:
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items:
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- const: core_clk
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- const: sclk_unipro_main
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phys:
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maxItems: 1
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phy-names:
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const: ufs-phy
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samsung,sysreg:
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2023-10-24 12:59:35 +02:00
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$ref: /schemas/types.yaml#/definitions/phandle-array
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2023-08-30 17:31:07 +02:00
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description: Should be phandle/offset pair. The phandle to the syscon node
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which indicates the FSYSx sysreg interface and the offset of
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the control register for UFS io coherency setting.
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dma-coherent: true
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required:
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- compatible
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- reg
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- phys
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- phy-names
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/exynos7-clk.h>
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ufs: ufs@15570000 {
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compatible = "samsung,exynos7-ufs";
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reg = <0x15570000 0x100>,
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<0x15570100 0x100>,
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<0x15571000 0x200>,
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<0x15572000 0x300>;
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reg-names = "hci", "vs_hci", "unipro", "ufsp";
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interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
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<&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
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clock-names = "core_clk", "sclk_unipro_main";
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pinctrl-names = "default";
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pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
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phys = <&ufs_phy>;
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phy-names = "ufs-phy";
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};
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...
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