2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Realtek Otto watchdog timer
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maintainers:
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- Sander Vanheule <sander@svanheule.net>
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description: |
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The timer has two timeout phases. Both phases have a maximum duration of 32
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prescaled clock ticks, which is ca. 43s with a bus clock of 200MHz. The
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minimum duration of each phase is one tick. Each phase can trigger an
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interrupt, although the phase 2 interrupt will occur with the system reset.
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- Phase 1: During this phase, the WDT can be pinged to reset the timeout.
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- Phase 2: Starts after phase 1 has timed out, and only serves to give the
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system some time to clean up, or notify others that it's going to reset.
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During this phase, pinging the WDT has no effect, and a reset is
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unavoidable, unless the WDT is disabled.
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allOf:
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- $ref: watchdog.yaml#
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properties:
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compatible:
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enum:
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- realtek,rtl8380-wdt
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- realtek,rtl8390-wdt
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- realtek,rtl9300-wdt
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- realtek,rtl9310-wdt
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupts:
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items:
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- description: interrupt specifier for pretimeout
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- description: interrupt specifier for timeout
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interrupt-names:
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items:
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- const: phase1
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- const: phase2
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realtek,reset-mode:
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$ref: /schemas/types.yaml#/definitions/string
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description: |
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Specify how the system is reset after a timeout. Defaults to "cpu" if
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left unspecified.
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oneOf:
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- description: Reset the entire chip
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const: soc
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- description: |
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Reset the CPU and IPsec engine, but leave other peripherals untouched
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const: cpu
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- description: |
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Reset the execution pointer, but don't actually reset any hardware
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const: software
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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2023-10-24 12:59:35 +02:00
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- interrupt-names
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2023-08-30 17:31:07 +02:00
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unevaluatedProperties: false
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examples:
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- |
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watchdog: watchdog@3150 {
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compatible = "realtek,rtl8380-wdt";
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reg = <0x3150 0xc>;
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realtek,reset-mode = "soc";
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clocks = <&lxbus_clock>;
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timeout-sec = <20>;
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interrupt-parent = <&rtlintc>;
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interrupt-names = "phase1", "phase2";
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interrupts = <19>, <18>;
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};
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...
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