231 lines
10 KiB
ReStructuredText
231 lines
10 KiB
ReStructuredText
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=======================
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Display Core Next (DCN)
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=======================
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To equip our readers with the basic knowledge of how AMD Display Core Next
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(DCN) works, we need to start with an overview of the hardware pipeline. Below
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you can see a picture that provides a DCN overview, keep in mind that this is a
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generic diagram, and we have variations per ASIC.
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.. kernel-figure:: dc_pipeline_overview.svg
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Based on this diagram, we can pass through each block and briefly describe
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them:
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* **Display Controller Hub (DCHUB)**: This is the gateway between the Scalable
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Data Port (SDP) and DCN. This component has multiple features, such as memory
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arbitration, rotation, and cursor manipulation.
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* **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
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processing such as color space conversion, linearization of pixel data, tone
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mapping, and gamut mapping.
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* **Multiple Pipe/Plane Combined (MPC)**: This component performs blending of
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multiple planes, using global or per-pixel alpha.
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* **Output Pixel Processing (OPP)**: Process and format pixels to be sent to
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the display.
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* **Output Pipe Timing Combiner (OPTC)**: It generates time output to combine
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streams or divide capabilities. CRC values are generated in this block.
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* **Display Output (DIO)**: Codify the output to the display connected to our
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GPU.
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* **Display Writeback (DWB)**: It provides the ability to write the output of
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the display pipe back to memory as video frames.
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* **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
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(Note that DWB is not hooked yet).
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* **DCN Management Unit (DMU)**: It provides registers with access control and
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interrupts the controller to the SOC host interrupt unit. This block includes
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the Display Micro-Controller Unit - version B (DMCUB), which is handled via
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firmware.
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* **DCN Clock Generator Block (DCCG)**: It provides the clocks and resets
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for all of the display controller clock domains.
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* **Azalia (AZ)**: Audio engine.
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The above diagram is an architecture generalization of DCN, which means that
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every ASIC has variations around this base model. Notice that the display
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pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you can see
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the SDP as the element from our Data Fabric that feeds the display pipe.
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Always approach the DCN architecture as something flexible that can be
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configured and reconfigured in multiple ways; in other words, each block can be
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setup or ignored accordingly with userspace demands. For example, if we
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want to drive an 8k@60Hz with a DSC enabled, our DCN may require 4 DPP and 2
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OPP. It is DC's responsibility to drive the best configuration for each
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specific scenario. Orchestrate all of these components together requires a
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sophisticated communication interface which is highlighted in the diagram by
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the edges that connect each block; from the chart, each connection between
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these blocks represents:
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1. Pixel data interface (red): Represents the pixel data flow;
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2. Global sync signals (green): It is a set of synchronization signals composed
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by VStartup, VUpdate, and VReady;
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3. Config interface: Responsible to configure blocks;
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4. Sideband signals: All other signals that do not fit the previous one.
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These signals are essential and play an important role in DCN. Nevertheless,
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the Global Sync deserves an extra level of detail described in the next
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section.
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All of these components are represented by a data structure named dc_state.
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From DCHUB to MPC, we have a representation called dc_plane; from MPC to OPTC,
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we have dc_stream, and the output (DIO) is handled by dc_link. Keep in mind
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that HUBP accesses a surface using a specific format read from memory, and our
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dc_plane should work to convert all pixels in the plane to something that can
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be sent to the display via dc_stream and dc_link.
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Front End and Back End
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----------------------
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Display pipeline can be broken down into two components that are usually
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referred as **Front End (FE)** and **Back End (BE)**, where FE consists of:
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* DCHUB (Mainly referring to a subcomponent named HUBP)
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* DPP
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* MPC
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On the other hand, BE consist of
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* OPP
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* OPTC
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* DIO (DP/HDMI stream encoder and link encoder)
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OPP and OPTC are two joining blocks between FE and BE. On a side note, this is
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a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
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to choose which link encoder to connect to which PHY. FE's main responsibility
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is to change, blend and compose pixel data, while BE's job is to frame a
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generic pixel stream to a specific display's pixel stream.
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Data Flow
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---------
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Initially, data is passed in from VRAM through Data Fabric (DF) in native pixel
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formats. Such data format stays through till HUBP in DCHUB, where HUBP unpacks
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different pixel formats and outputs them to DPP in uniform streams through 4
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channels (1 for alpha + 3 for colors).
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The Converter and Cursor (CNVC) in DPP would then normalize the data
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representation and convert them to a DCN specific floating-point format (i.e.,
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different from the IEEE floating-point format). In the process, CNVC also
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applies a degamma function to transform the data from non-linear to linear
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space to relax the floating-point calculations following. Data would stay in
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this floating-point format from DPP to OPP.
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Starting OPP, because color transformation and blending have been completed
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(i.e alpha can be dropped), and the end sinks do not require the precision and
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dynamic range that floating points provide (i.e. all displays are in integer
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depth format), bit-depth reduction/dithering would kick in. In OPP, we would
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also apply a regamma function to introduce the gamma removed earlier back.
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Eventually, we output data in integer format at DIO.
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AMD Hardware Pipeline
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---------------------
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When discussing graphics on Linux, the **pipeline** term can sometimes be
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overloaded with multiple meanings, so it is important to define what we mean
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when we say **pipeline**. In the DCN driver, we use the term **hardware
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pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a
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sequence of DCN blocks instantiated to address some specific configuration. DC
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core treats DCN blocks as individual resources, meaning we can build a pipeline
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by taking resources for all individual hardware blocks to compose one pipeline.
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In actuality, we can't connect an arbitrary block from one pipe to a block from
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another pipe; they are routed linearly, except for DSC, which can be
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arbitrarily assigned as needed. We have this pipeline concept for trying to
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optimize bandwidth utilization.
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.. kernel-figure:: pipeline_4k_no_split.svg
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Additionally, let's take a look at parts of the DTN log (see
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'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
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this log can help us to see part of this pipeline behavior in real-time::
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HUBP: format addr_hi width height ...
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[ 0]: 8h 81h 3840 2160
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[ 1]: 0h 0h 0 0
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[ 2]: 0h 0h 0 0
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[ 3]: 0h 0h 0 0
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[ 4]: 0h 0h 0 0
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...
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MPCC: OPP DPP ...
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[ 0]: 0h 0h ...
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The first thing to notice from the diagram and DTN log it is the fact that we
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have different clock domains for each part of the DCN blocks. In this example,
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we have just a single **pipeline** where the data flows from DCHUB to DIO, as
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we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and
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we can split this single pipe differently, as described in the below diagram:
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.. kernel-figure:: pipeline_4k_split.svg
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Now, if we inspect the DTN log again we can see some interesting changes::
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HUBP: format addr_hi width height ...
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[ 0]: 8h 81h 1920 2160 ...
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...
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[ 4]: 0h 0h 0 0 ...
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[ 5]: 8h 81h 1920 2160 ...
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...
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MPCC: OPP DPP ...
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[ 0]: 0h 0h ...
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[ 5]: 0h 5h ...
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From the above example, we now split the display pipeline into two vertical
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parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the
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clock frequency in the DPP part. This is not only useful for saving power but
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also to better handle the required throughput. The idea to keep in mind here is
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that the pipe configuration can vary a lot according to the display
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configuration, and it is the DML's responsibility to set up all required
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configuration parameters for multiple scenarios supported by our hardware.
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Global Sync
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-----------
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Many DCN registers are double buffered, most importantly the surface address.
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This allows us to update DCN hardware atomically for page flips, as well as
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for most other updates that don't require enabling or disabling of new pipes.
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(Note: There are many scenarios when DC will decide to reserve extra pipes
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in order to support outputs that need a very high pixel clock, or for
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power saving purposes.)
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These atomic register updates are driven by global sync signals in DCN. In
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order to understand how atomic updates interact with DCN hardware, and how DCN
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signals page flip and vblank events it is helpful to understand how global sync
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is programmed.
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Global sync consists of three signals, VSTARTUP, VUPDATE, and VREADY. These are
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calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml)
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based on a large number of parameters and ensure our hardware is able to feed
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the DCN pipeline without underflows or hangs in any given system configuration.
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The global sync signals always happen during VBlank, are independent from the
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VSync signal, and do not overlap each other.
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VUPDATE is the only signal that is of interest to the rest of the driver stack
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or userspace clients as it signals the point at which hardware latches to
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atomically programmed (i.e. double buffered) registers. Even though it is
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independent of the VSync signal we use VUPDATE to signal the VSync event as it
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provides the best indication of how atomic commits and hardware interact.
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Since DCN hardware is double-buffered the DC driver is able to program the
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hardware at any point during the frame.
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The below picture illustrates the global sync signals:
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.. kernel-figure:: global_sync_vblank.svg
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These signals affect core DCN behavior. Programming them incorrectly will lead
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to a number of negative consequences, most of them quite catastrophic.
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The following picture shows how global sync allows for a mailbox style of
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updates, i.e. it allows for multiple re-configurations between VUpdate
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events where only the last configuration programmed before the VUpdate signal
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becomes effective.
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.. kernel-figure:: config_example.svg
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