219 lines
8.2 KiB
ReStructuredText
219 lines
8.2 KiB
ReStructuredText
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.. SPDX-License-Identifier: GPL-2.0
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==========================
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MHI (Modem Host Interface)
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==========================
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This document provides information about the MHI protocol.
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Overview
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========
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MHI is a protocol developed by Qualcomm Innovation Center, Inc. It is used
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by the host processors to control and communicate with modem devices over high
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speed peripheral buses or shared memory. Even though MHI can be easily adapted
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to any peripheral buses, it is primarily used with PCIe based devices. MHI
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provides logical channels over the physical buses and allows transporting the
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modem protocols, such as IP data packets, modem control messages, and
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diagnostics over at least one of those logical channels. Also, the MHI
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protocol provides data acknowledgment feature and manages the power state of the
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modems via one or more logical channels.
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MHI Internals
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=============
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MMIO
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----
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MMIO (Memory mapped IO) consists of a set of registers in the device hardware,
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which are mapped to the host memory space by the peripheral buses like PCIe.
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Following are the major components of MMIO register space:
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MHI control registers: Access to MHI configurations registers
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MHI BHI registers: BHI (Boot Host Interface) registers are used by the host
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for downloading the firmware to the device before MHI initialization.
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Channel Doorbell array: Channel Doorbell (DB) registers used by the host to
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notify the device when there is new work to do.
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Event Doorbell array: Associated with event context array, the Event Doorbell
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(DB) registers are used by the host to notify the device when new events are
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available.
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Debug registers: A set of registers and counters used by the device to expose
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debugging information like performance, functional, and stability to the host.
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Data structures
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---------------
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All data structures used by MHI are in the host system memory. Using the
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physical interface, the device accesses those data structures. MHI data
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structures and data buffers in the host system memory regions are mapped for
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the device.
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Channel context array: All channel configurations are organized in channel
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context data array.
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Transfer rings: Used by the host to schedule work items for a channel. The
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transfer rings are organized as a circular queue of Transfer Descriptors (TD).
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Event context array: All event configurations are organized in the event context
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data array.
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Event rings: Used by the device to send completion and state transition messages
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to the host
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Command context array: All command configurations are organized in command
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context data array.
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Command rings: Used by the host to send MHI commands to the device. The command
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rings are organized as a circular queue of Command Descriptors (CD).
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Channels
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--------
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MHI channels are logical, unidirectional data pipes between a host and a device.
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The concept of channels in MHI is similar to endpoints in USB. MHI supports up
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to 256 channels. However, specific device implementations may support less than
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the maximum number of channels allowed.
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Two unidirectional channels with their associated transfer rings form a
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bidirectional data pipe, which can be used by the upper-layer protocols to
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transport application data packets (such as IP packets, modem control messages,
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diagnostics messages, and so on). Each channel is associated with a single
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transfer ring.
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Transfer rings
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--------------
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Transfers between the host and device are organized by channels and defined by
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Transfer Descriptors (TD). TDs are managed through transfer rings, which are
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defined for each channel between the device and host and reside in the host
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memory. TDs consist of one or more ring elements (or transfer blocks)::
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[Read Pointer (RP)] ----------->[Ring Element] } TD
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[Write Pointer (WP)]- [Ring Element]
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- [Ring Element]
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--------->[Ring Element]
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[Ring Element]
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Below is the basic usage of transfer rings:
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* Host allocates memory for transfer ring.
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* Host sets the base pointer, read pointer, and write pointer in corresponding
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channel context.
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* Ring is considered empty when RP == WP.
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* Ring is considered full when WP + 1 == RP.
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* RP indicates the next element to be serviced by the device.
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* When the host has a new buffer to send, it updates the ring element with
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buffer information, increments the WP to the next element and rings the
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associated channel DB.
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Event rings
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-----------
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Events from the device to host are organized in event rings and defined by Event
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Descriptors (ED). Event rings are used by the device to report events such as
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data transfer completion status, command completion status, and state changes
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to the host. Event rings are the array of EDs that resides in the host
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memory. EDs consist of one or more ring elements (or transfer blocks)::
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[Read Pointer (RP)] ----------->[Ring Element] } ED
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[Write Pointer (WP)]- [Ring Element]
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- [Ring Element]
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--------->[Ring Element]
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[Ring Element]
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Below is the basic usage of event rings:
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* Host allocates memory for event ring.
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* Host sets the base pointer, read pointer, and write pointer in corresponding
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channel context.
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* Both host and device has a local copy of RP, WP.
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* Ring is considered empty (no events to service) when WP + 1 == RP.
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* Ring is considered full of events when RP == WP.
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* When there is a new event the device needs to send, the device updates ED
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pointed by RP, increments the RP to the next element and triggers the
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interrupt.
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Ring Element
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------------
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A Ring Element is a data structure used to transfer a single block
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of data between the host and the device. Transfer ring element types contain a
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single buffer pointer, the size of the buffer, and additional control
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information. Other ring element types may only contain control and status
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information. For single buffer operations, a ring descriptor is composed of a
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single element. For large multi-buffer operations (such as scatter and gather),
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elements can be chained to form a longer descriptor.
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MHI Operations
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==============
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MHI States
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----------
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MHI_STATE_RESET
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~~~~~~~~~~~~~~~
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MHI is in reset state after power-up or hardware reset. The host is not allowed
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to access device MMIO register space.
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MHI_STATE_READY
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~~~~~~~~~~~~~~~
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MHI is ready for initialization. The host can start MHI initialization by
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programming MMIO registers.
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MHI_STATE_M0
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~~~~~~~~~~~~
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MHI is running and operational in the device. The host can start channels by
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issuing channel start command.
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MHI_STATE_M1
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~~~~~~~~~~~~
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MHI operation is suspended by the device. This state is entered when the
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device detects inactivity at the physical interface within a preset time.
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MHI_STATE_M2
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~~~~~~~~~~~~
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MHI is in low power state. MHI operation is suspended and the device may
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enter lower power mode.
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MHI_STATE_M3
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~~~~~~~~~~~~
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MHI operation stopped by the host. This state is entered when the host suspends
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MHI operation.
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MHI Initialization
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------------------
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After system boots, the device is enumerated over the physical interface.
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In the case of PCIe, the device is enumerated and assigned BAR-0 for
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the device's MMIO register space. To initialize the MHI in a device,
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the host performs the following operations:
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* Allocates the MHI context for event, channel and command arrays.
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* Initializes the context array, and prepares interrupts.
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* Waits until the device enters READY state.
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* Programs MHI MMIO registers and sets device into MHI_M0 state.
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* Waits for the device to enter M0 state.
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MHI Data Transfer
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-----------------
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MHI data transfer is initiated by the host to transfer data to the device.
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Following are the sequence of operations performed by the host to transfer
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data to device:
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* Host prepares TD with buffer information.
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* Host increments the WP of the corresponding channel transfer ring.
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* Host rings the channel DB register.
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* Device wakes up to process the TD.
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* Device generates a completion event for the processed TD by updating ED.
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* Device increments the RP of the corresponding event ring.
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* Device triggers IRQ to wake up the host.
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* Host wakes up and checks the event ring for completion event.
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* Host updates the WP of the corresponding event ring to indicate that the
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data transfer has been completed successfully.
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