233 lines
6.0 KiB
Plaintext
233 lines
6.0 KiB
Plaintext
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/*
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* Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Antoine Tenart <antoine.tenart@free-electrons.com>
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Annapurna Labs Alpine v2";
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compatible = "al,alpine-v2";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a57";
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device_type = "cpu";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu@1 {
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compatible = "arm,cortex-a57";
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device_type = "cpu";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu@2 {
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compatible = "arm,cortex-a57";
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device_type = "cpu";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu@3 {
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compatible = "arm,cortex-a57";
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device_type = "cpu";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-0.2", "arm,psci";
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method = "smc";
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cpu_suspend = <0x84000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0x84000003>;
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};
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sbclk: sbclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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ranges;
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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};
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gic: interrupt-controller@f0200000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */
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<0x0 0xf0280000 0x0 0x200000>, /* GICR */
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<0x0 0xf0100000 0x0 0x2000>, /* GICC */
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<0x0 0xf0110000 0x0 0x2000>, /* GICV */
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<0x0 0xf0120000 0x0 0x2000>; /* GICH */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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pci@fbc00000 {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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#interrupt-cells = <1>;
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reg = <0x0 0xfbc00000 0x0 0x100000>;
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interrupt-map-mask = <0xf800 0 0 7>;
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/* add legacy interrupts for SATA only */
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interrupt-map = <0x4000 0 0 1 &gic 0 53 4>,
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<0x4800 0 0 1 &gic 0 54 4>;
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/* 32 bit non prefetchable memory space */
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ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
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bus-range = <0x00 0x00>;
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msi-parent = <&msix>;
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};
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msix: msix@fbe00000 {
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compatible = "al,alpine-msix";
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reg = <0x0 0xfbe00000 0x0 0x100000>;
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interrupt-controller;
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msi-controller;
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al,msi-base-spi = <160>;
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al,msi-num-spis = <160>;
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};
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io-fabric {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0xfc000000 0x2000000>;
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uart0: serial@1883000 {
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compatible = "ns16550a";
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reg = <0x1883000 0x1000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <500000000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart1: serial@1884000 {
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compatible = "ns16550a";
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reg = <0x1884000 0x1000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <500000000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@1885000 {
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compatible = "ns16550a";
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reg = <0x1885000 0x1000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <500000000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@1886000 {
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compatible = "ns16550a";
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reg = <0x1886000 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <500000000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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timer0: timer@1890000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x1890000 0x1000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sbclk>;
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};
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timer1: timer@1891000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x1891000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sbclk>;
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status = "disabled";
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};
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timer2: timer@1892000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x1892000 0x1000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sbclk>;
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status = "disabled";
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};
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timer3: timer@1893000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x1893000 0x1000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sbclk>;
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status = "disabled";
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};
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};
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};
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};
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