286 lines
7.1 KiB
Plaintext
286 lines
7.1 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/*
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* DTS file for AMD Seattle SoC
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*
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* Copyright (C) 2014 Advanced Micro Devices, Inc.
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*/
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/ {
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compatible = "amd,seattle";
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interrupt-parent = <&gic0>;
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#address-cells = <2>;
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#size-cells = <2>;
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gic0: interrupt-controller@e1101000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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reg = <0x0 0xe1110000 0 0x1000>,
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<0x0 0xe112f000 0 0x2000>,
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<0x0 0xe1140000 0 0x2000>,
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<0x0 0xe1160000 0 0x2000>;
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interrupts = <1 9 0xf04>;
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ranges = <0 0 0 0xe1100000 0 0x100000>;
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v2m0: v2m@e0080000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x00080000 0 0x1000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xff04>,
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<1 14 0xff04>,
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<1 11 0xff04>,
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<1 10 0xff04>;
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};
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smb0: smb {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/*
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* dma-ranges is 40-bit address space containing:
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* - GICv2m MSI register is at 0xe0080000
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* - DRAM range [0x8000000000 to 0xffffffffff]
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*/
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dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
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/include/ "amd-seattle-clks.dtsi"
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sata0: sata@e0300000 {
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compatible = "snps,dwc-ahci";
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reg = <0 0xe0300000 0 0xf0000>;
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interrupts = <0 355 4>;
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clocks = <&sataclk_333mhz>;
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iommus = <&sata0_smmu 0x0 0x1f>;
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dma-coherent;
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};
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/* This is for Rev B only */
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sata1: sata@e0d00000 {
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status = "disabled";
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compatible = "snps,dwc-ahci";
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reg = <0 0xe0d00000 0 0xf0000>;
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interrupts = <0 354 4>;
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clocks = <&sataclk_333mhz>;
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iommus = <&sata1_smmu 0x0e>,
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<&sata1_smmu 0x0f>,
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<&sata1_smmu 0x1e>;
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dma-coherent;
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};
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sata0_smmu: iommu@e0200000 {
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compatible = "arm,mmu-401";
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reg = <0 0xe0200000 0 0x10000>;
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#global-interrupts = <1>;
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interrupts = <0 332 4>, <0 332 4>;
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#iommu-cells = <2>;
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dma-coherent;
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};
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sata1_smmu: iommu@e0c00000 {
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compatible = "arm,mmu-401";
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reg = <0 0xe0c00000 0 0x10000>;
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#global-interrupts = <1>;
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interrupts = <0 331 4>, <0 331 4>;
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#iommu-cells = <1>;
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dma-coherent;
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};
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i2c0: i2c@e1000000 {
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status = "disabled";
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compatible = "snps,designware-i2c";
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reg = <0 0xe1000000 0 0x1000>;
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interrupts = <0 357 4>;
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clocks = <&miscclk_250mhz>;
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};
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i2c1: i2c@e0050000 {
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status = "disabled";
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compatible = "snps,designware-i2c";
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reg = <0 0xe0050000 0 0x1000>;
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interrupts = <0 340 4>;
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clocks = <&miscclk_250mhz>;
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};
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serial0: serial@e1010000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0xe1010000 0 0x1000>;
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interrupts = <0 328 4>;
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clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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spi0: spi@e1020000 {
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status = "disabled";
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compatible = "arm,pl022", "arm,primecell";
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reg = <0 0xe1020000 0 0x1000>;
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spi-controller;
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interrupts = <0 330 4>;
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clocks = <&uartspiclk_100mhz>;
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clock-names = "apb_pclk";
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};
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spi1: spi@e1030000 {
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status = "disabled";
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compatible = "arm,pl022", "arm,primecell";
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reg = <0 0xe1030000 0 0x1000>;
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spi-controller;
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interrupts = <0 329 4>;
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clocks = <&uartspiclk_100mhz>;
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clock-names = "apb_pclk";
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gpio0: gpio@e1040000 { /* Not available to OS for B0 */
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status = "disabled";
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compatible = "arm,pl061", "arm,primecell";
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#gpio-cells = <2>;
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reg = <0 0xe1040000 0 0x1000>;
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gpio-controller;
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interrupts = <0 359 4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&miscclk_250mhz>;
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clock-names = "apb_pclk";
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};
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gpio1: gpio@e1050000 { /* [0:7] */
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status = "disabled";
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compatible = "arm,pl061", "arm,primecell";
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#gpio-cells = <2>;
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reg = <0 0xe1050000 0 0x1000>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 358 4>;
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clocks = <&miscclk_250mhz>;
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clock-names = "apb_pclk";
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};
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gpio2: gpio@e0020000 { /* [8:15] */
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status = "disabled";
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compatible = "arm,pl061", "arm,primecell";
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#gpio-cells = <2>;
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reg = <0 0xe0020000 0 0x1000>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 366 4>;
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clocks = <&miscclk_250mhz>;
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clock-names = "apb_pclk";
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};
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gpio3: gpio@e0030000 { /* [16:23] */
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status = "disabled";
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compatible = "arm,pl061", "arm,primecell";
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#gpio-cells = <2>;
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reg = <0 0xe0030000 0 0x1000>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 365 4>;
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clocks = <&miscclk_250mhz>;
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clock-names = "apb_pclk";
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};
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gpio4: gpio@e0080000 { /* [24] */
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status = "disabled";
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compatible = "arm,pl061", "arm,primecell";
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#gpio-cells = <2>;
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reg = <0 0xe0080000 0 0x1000>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 361 4>;
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clocks = <&miscclk_250mhz>;
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clock-names = "apb_pclk";
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};
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ccp0: ccp@e0100000 {
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status = "disabled";
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compatible = "amd,ccp-seattle-v1a";
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reg = <0 0xe0100000 0 0x10000>;
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interrupts = <0 3 4>;
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dma-coherent;
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iommus = <&sata1_smmu 0x00>,
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<&sata1_smmu 0x02>,
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<&sata1_smmu 0x40>,
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<&sata1_smmu 0x42>;
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};
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pcie0: pcie@f0000000 {
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compatible = "pci-host-ecam-generic";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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bus-range = <0 0x7f>;
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msi-parent = <&v2m0>;
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reg = <0 0xf0000000 0 0x10000000>;
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interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
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interrupt-map =
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<0x1100 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
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<0x1100 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
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<0x1100 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
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<0x1100 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>,
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<0x1200 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x124 0x1>,
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<0x1200 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x125 0x1>,
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<0x1200 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x126 0x1>,
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<0x1200 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x127 0x1>,
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<0x1300 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x128 0x1>,
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<0x1300 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x129 0x1>,
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<0x1300 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x12a 0x1>,
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<0x1300 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x12b 0x1>;
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dma-coherent;
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dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
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ranges =
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/* I/O Memory (size=64K) */
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<0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
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/* 32-bit MMIO (size=2G) */
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<0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
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/* 64-bit MMIO (size= 508G) */
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<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
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iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
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};
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pcie_smmu: iommu@e0a00000 {
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compatible = "arm,mmu-401";
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reg = <0 0xe0a00000 0 0x10000>;
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#global-interrupts = <1>;
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interrupts = <0 333 4>, <0 333 4>;
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#iommu-cells = <1>;
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dma-coherent;
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};
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/* Perf CCN504 PMU */
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ccn: ccn@e8000000 {
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compatible = "arm,ccn-504";
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reg = <0x0 0xe8000000 0 0x1000000>;
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interrupts = <0 380 4>;
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};
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ipmi_kcs: kcs@e0010000 {
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status = "disabled";
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compatible = "ipmi-kcs";
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device_type = "ipmi";
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reg = <0x0 0xe0010000 0 0x8>;
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interrupts = <0 389 4>;
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reg-size = <1>;
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reg-spacing = <4>;
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};
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};
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};
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