113 lines
2.5 KiB
Plaintext
113 lines
2.5 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rk3568-fastrhino-r66s.dtsi"
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/ {
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model = "Lunzn FastRhino R68S";
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compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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mmc0 = &sdhci;
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};
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adc-keys {
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compatible = "adc-keys";
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io-channels = <&saradc 0>;
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io-channel-names = "buttons";
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keyup-threshold-microvolt = <1800000>;
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button-recovery {
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label = "Recovery";
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linux,code = <KEY_VENDOR>;
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press-threshold-microvolt = <1750>;
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};
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};
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};
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&gmac0 {
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assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
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assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
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assigned-clock-rates = <0>, <125000000>;
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clock_in_out = "output";
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phy-handle = <&rgmii_phy0>;
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&gmac0_miim
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&gmac0_tx_bus2
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&gmac0_rx_bus2
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&gmac0_rgmii_clk
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&gmac0_rgmii_bus>;
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snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 15ms, 50ms for rtl8211f */
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snps,reset-delays-us = <0 15000 50000>;
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tx_delay = <0x3c>;
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rx_delay = <0x2f>;
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status = "okay";
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};
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&gmac1 {
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assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
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assigned-clock-rates = <0>, <125000000>;
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clock_in_out = "output";
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phy-handle = <&rgmii_phy1>;
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1m1_miim
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&gmac1m1_tx_bus2
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&gmac1m1_rx_bus2
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&gmac1m1_rgmii_clk
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&gmac1m1_rgmii_bus>;
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snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 15ms, 50ms for rtl8211f */
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snps,reset-delays-us = <0 15000 50000>;
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tx_delay = <0x4f>;
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rx_delay = <0x26>;
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status = "okay";
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};
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&mdio0 {
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rgmii_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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pinctrl-0 = <ð_phy0_reset_pin>;
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pinctrl-names = "default";
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};
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};
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&mdio1 {
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rgmii_phy1: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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pinctrl-0 = <ð_phy1_reset_pin>;
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pinctrl-names = "default";
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};
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};
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&pinctrl {
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gmac0 {
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eth_phy0_reset_pin: eth-phy0-reset-pin {
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rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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gmac1 {
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eth_phy1_reset_pin: eth-phy1-reset-pin {
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rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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};
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&sdhci {
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bus-width = <8>;
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max-frequency = <200000000>;
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non-removable;
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
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status = "okay";
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};
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