113 lines
2.4 KiB
Plaintext
113 lines
2.4 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
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* (http://www.friendlyelec.com)
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*
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* Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
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*/
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/dts-v1/;
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#include "rk3568-nanopi-r5s.dtsi"
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/ {
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model = "FriendlyElec NanoPi R5C";
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compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&reset_button_pin>;
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button-reset {
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debounce-interval = <50>;
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gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
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label = "reset";
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linux,code = <KEY_RESTART>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
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led-lan {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
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};
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power_led: led-power {
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_POWER;
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linux,default-trigger = "heartbeat";
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gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
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};
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led-wan {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_WAN;
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gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
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};
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led-wlan {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_WLAN;
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gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&pcie2x1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie20_reset_pin>;
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reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&pcie3x1 {
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num-lanes = <1>;
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reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie>;
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status = "okay";
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};
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&pcie3x2 {
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num-lanes = <1>;
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reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie>;
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status = "okay";
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};
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&pinctrl {
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gpio-leds {
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lan_led_pin: lan-led-pin {
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rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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power_led_pin: power-led-pin {
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rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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wan_led_pin: wan-led-pin {
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rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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wlan_led_pin: wlan-led-pin {
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rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pcie {
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pcie20_reset_pin: pcie20-reset-pin {
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rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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rockchip-key {
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reset_button_pin: reset-button-pin {
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rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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};
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