2023-08-30 16:31:07 +01:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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2023-10-24 11:59:35 +01:00
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/*
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* Hint encoding:
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*
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* Bit4: ordering or completion (0: completion, 1: ordering)
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* Bit3: barrier for previous read (0: true, 1: false)
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* Bit2: barrier for previous write (0: true, 1: false)
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* Bit1: barrier for succeeding read (0: true, 1: false)
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* Bit0: barrier for succeeding write (0: true, 1: false)
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*
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* Hint 0x700: barrier for "read after read" from the same address
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*/
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#define DBAR(hint) __asm__ __volatile__("dbar %0 " : : "I"(hint) : "memory")
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#define crwrw 0b00000
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#define cr_r_ 0b00101
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#define c_w_w 0b01010
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2023-08-30 16:31:07 +01:00
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2023-10-24 11:59:35 +01:00
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#define orwrw 0b10000
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#define or_r_ 0b10101
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#define o_w_w 0b11010
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2023-08-30 16:31:07 +01:00
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2023-10-24 11:59:35 +01:00
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#define orw_w 0b10010
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#define or_rw 0b10100
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2023-08-30 16:31:07 +01:00
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2023-10-24 11:59:35 +01:00
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#define c_sync() DBAR(crwrw)
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#define c_rsync() DBAR(cr_r_)
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#define c_wsync() DBAR(c_w_w)
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#define o_sync() DBAR(orwrw)
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#define o_rsync() DBAR(or_r_)
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#define o_wsync() DBAR(o_w_w)
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#define ldacq_mb() DBAR(or_rw)
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#define strel_mb() DBAR(orw_w)
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#define mb() c_sync()
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#define rmb() c_rsync()
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#define wmb() c_wsync()
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#define iob() c_sync()
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#define wbflush() c_sync()
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#define __smp_mb() o_sync()
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#define __smp_rmb() o_rsync()
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#define __smp_wmb() o_wsync()
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2023-08-30 16:31:07 +01:00
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#ifdef CONFIG_SMP
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2023-10-24 11:59:35 +01:00
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#define __WEAK_LLSC_MB " dbar 0x700 \n"
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2023-08-30 16:31:07 +01:00
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#else
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2023-10-24 11:59:35 +01:00
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#define __WEAK_LLSC_MB " \n"
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2023-08-30 16:31:07 +01:00
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#endif
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#define __smp_mb__before_atomic() barrier()
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#define __smp_mb__after_atomic() barrier()
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/**
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* array_index_mask_nospec() - generate a ~0 mask when index < size, 0 otherwise
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* @index: array element index
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* @size: number of elements in array
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*
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* Returns:
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* 0 - (@index < @size)
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*/
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#define array_index_mask_nospec array_index_mask_nospec
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static inline unsigned long array_index_mask_nospec(unsigned long index,
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unsigned long size)
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{
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unsigned long mask;
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__asm__ __volatile__(
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"sltu %0, %1, %2\n\t"
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#if (__SIZEOF_LONG__ == 4)
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"sub.w %0, $zero, %0\n\t"
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#elif (__SIZEOF_LONG__ == 8)
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"sub.d %0, $zero, %0\n\t"
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#endif
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: "=r" (mask)
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: "r" (index), "r" (size)
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:);
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return mask;
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}
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2023-10-24 11:59:35 +01:00
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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ldacq_mb(); \
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___p1; \
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})
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2023-10-24 11:59:35 +01:00
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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strel_mb(); \
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WRITE_ONCE(*p, v); \
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2023-08-30 16:31:07 +01:00
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} while (0)
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#define __smp_store_mb(p, v) \
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do { \
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union { typeof(p) __val; char __c[1]; } __u = \
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{ .__val = (__force typeof(p)) (v) }; \
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unsigned long __tmp; \
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switch (sizeof(p)) { \
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case 1: \
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*(volatile __u8 *)&p = *(__u8 *)__u.__c; \
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__smp_mb(); \
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break; \
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case 2: \
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*(volatile __u16 *)&p = *(__u16 *)__u.__c; \
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__smp_mb(); \
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break; \
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case 4: \
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__asm__ __volatile__( \
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"amswap_db.w %[tmp], %[val], %[mem] \n" \
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: [mem] "+ZB" (*(u32 *)&p), [tmp] "=&r" (__tmp) \
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: [val] "r" (*(__u32 *)__u.__c) \
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: ); \
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break; \
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case 8: \
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__asm__ __volatile__( \
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"amswap_db.d %[tmp], %[val], %[mem] \n" \
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: [mem] "+ZB" (*(u64 *)&p), [tmp] "=&r" (__tmp) \
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: [val] "r" (*(__u64 *)__u.__c) \
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: ); \
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break; \
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} \
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} while (0)
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#include <asm-generic/barrier.h>
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#endif /* __ASM_BARRIER_H */
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