219 lines
5.6 KiB
ArmAsm
219 lines
5.6 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2018, IBM Corporation.
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*
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* This file contains general idle entry/exit functions to save
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* and restore stack and NVGPRs which allows C code to call idle
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* states that lose GPRs, and it will return transparently with
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* SRR1 wakeup reason return value.
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*
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* The platform / CPU caller must ensure SPRs and any other non-GPR
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* state is saved and restored correctly, handle KVM, interrupts, etc.
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*/
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ppc-opcode.h>
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#include <asm/cpuidle.h>
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#include <asm/thread_info.h> /* TLF_NAPPING */
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#ifdef CONFIG_PPC_P7_NAP
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/*
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* Desired PSSCR in r3
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*
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* No state will be lost regardless of wakeup mechanism (interrupt or NIA).
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*
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* An EC=0 type wakeup will return with a value of 0. SRESET wakeup (which can
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* happen with xscom SRESET and possibly MCE) may clobber volatiles except LR,
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* and must blr, to return to caller with r3 set according to caller's expected
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* return code (for Book3S/64 that is SRR1).
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*/
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_GLOBAL(isa300_idle_stop_noloss)
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mtspr SPRN_PSSCR,r3
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PPC_STOP
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li r3,0
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blr
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/*
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* Desired PSSCR in r3
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*
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* GPRs may be lost, so they are saved here. Wakeup is by interrupt only.
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* The SRESET wakeup returns to this function's caller by calling
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* idle_return_gpr_loss with r3 set to desired return value.
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*
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* A wakeup without GPR loss may alteratively be handled as in
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* isa300_idle_stop_noloss and blr directly, as an optimisation.
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*
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* The caller is responsible for saving/restoring SPRs, MSR, timebase,
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* etc.
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*/
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_GLOBAL(isa300_idle_stop_mayloss)
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mtspr SPRN_PSSCR,r3
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std r1,PACAR1(r13)
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mflr r4
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mfcr r5
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/*
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* Use the stack red zone rather than a new frame for saving regs since
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* in the case of no GPR loss the wakeup code branches directly back to
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* the caller without deallocating the stack frame first.
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*/
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std r2,-8*1(r1)
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std r14,-8*2(r1)
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std r15,-8*3(r1)
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std r16,-8*4(r1)
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std r17,-8*5(r1)
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std r18,-8*6(r1)
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std r19,-8*7(r1)
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std r20,-8*8(r1)
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std r21,-8*9(r1)
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std r22,-8*10(r1)
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std r23,-8*11(r1)
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std r24,-8*12(r1)
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std r25,-8*13(r1)
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std r26,-8*14(r1)
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std r27,-8*15(r1)
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std r28,-8*16(r1)
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std r29,-8*17(r1)
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std r30,-8*18(r1)
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std r31,-8*19(r1)
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std r4,-8*20(r1)
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std r5,-8*21(r1)
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/* 168 bytes */
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PPC_STOP
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b . /* catch bugs */
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/*
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* Desired return value in r3
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*
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* The idle wakeup SRESET interrupt can call this after calling
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* to return to the idle sleep function caller with r3 as the return code.
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*
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* This must not be used if idle was entered via a _noloss function (use
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* a simple blr instead).
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*/
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_GLOBAL(idle_return_gpr_loss)
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ld r1,PACAR1(r13)
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ld r4,-8*20(r1)
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ld r5,-8*21(r1)
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mtlr r4
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mtcr r5
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/*
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* KVM nap requires r2 to be saved, rather than just restoring it
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* from PACATOC. This could be avoided for that less common case
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* if KVM saved its r2.
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*/
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ld r2,-8*1(r1)
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ld r14,-8*2(r1)
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ld r15,-8*3(r1)
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ld r16,-8*4(r1)
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ld r17,-8*5(r1)
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ld r18,-8*6(r1)
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ld r19,-8*7(r1)
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ld r20,-8*8(r1)
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ld r21,-8*9(r1)
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ld r22,-8*10(r1)
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ld r23,-8*11(r1)
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ld r24,-8*12(r1)
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ld r25,-8*13(r1)
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ld r26,-8*14(r1)
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ld r27,-8*15(r1)
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ld r28,-8*16(r1)
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ld r29,-8*17(r1)
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ld r30,-8*18(r1)
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ld r31,-8*19(r1)
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blr
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/*
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* This is the sequence required to execute idle instructions, as
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* specified in ISA v2.07 (and earlier). MSR[IR] and MSR[DR] must be 0.
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* We have to store a GPR somewhere, ptesync, then reload it, and create
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* a false dependency on the result of the load. It doesn't matter which
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* GPR we store, or where we store it. We have already stored r2 to the
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* stack at -8(r1) in isa206_idle_insn_mayloss, so use that.
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*/
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#define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \
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/* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
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std r2,-8(r1); \
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ptesync; \
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ld r2,-8(r1); \
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236: cmpd cr0,r2,r2; \
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bne 236b; \
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IDLE_INST; \
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b . /* catch bugs */
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/*
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* Desired instruction type in r3
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*
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* GPRs may be lost, so they are saved here. Wakeup is by interrupt only.
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* The SRESET wakeup returns to this function's caller by calling
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* idle_return_gpr_loss with r3 set to desired return value.
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*
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* A wakeup without GPR loss may alteratively be handled as in
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* isa300_idle_stop_noloss and blr directly, as an optimisation.
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*
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* The caller is responsible for saving/restoring SPRs, MSR, timebase,
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* etc.
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*
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* This must be called in real-mode (MSR_IDLE).
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*/
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_GLOBAL(isa206_idle_insn_mayloss)
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std r1,PACAR1(r13)
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mflr r4
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mfcr r5
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/*
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* Use the stack red zone rather than a new frame for saving regs since
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* in the case of no GPR loss the wakeup code branches directly back to
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* the caller without deallocating the stack frame first.
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*/
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std r2,-8*1(r1)
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std r14,-8*2(r1)
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std r15,-8*3(r1)
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std r16,-8*4(r1)
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std r17,-8*5(r1)
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std r18,-8*6(r1)
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std r19,-8*7(r1)
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std r20,-8*8(r1)
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std r21,-8*9(r1)
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std r22,-8*10(r1)
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std r23,-8*11(r1)
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std r24,-8*12(r1)
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std r25,-8*13(r1)
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std r26,-8*14(r1)
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std r27,-8*15(r1)
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std r28,-8*16(r1)
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std r29,-8*17(r1)
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std r30,-8*18(r1)
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std r31,-8*19(r1)
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std r4,-8*20(r1)
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std r5,-8*21(r1)
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cmpwi r3,PNV_THREAD_NAP
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bne 1f
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IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
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1: cmpwi r3,PNV_THREAD_SLEEP
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bne 2f
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IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
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2: IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
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#endif
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#ifdef CONFIG_PPC_970_NAP
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_GLOBAL(power4_idle_nap)
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LOAD_REG_IMMEDIATE(r7, MSR_KERNEL|MSR_EE|MSR_POW)
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ld r9,PACA_THREAD_INFO(r13)
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ld r8,TI_LOCAL_FLAGS(r9)
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ori r8,r8,_TLF_NAPPING
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std r8,TI_LOCAL_FLAGS(r9)
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/*
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* NAPPING bit is set, from this point onward power4_fixup_nap
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* will cause exceptions to return to power4_idle_nap_return.
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*/
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1: sync
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isync
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mtmsrd r7
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isync
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b 1b
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.globl power4_idle_nap_return
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power4_idle_nap_return:
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blr
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#endif
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