265 lines
8.4 KiB
C
265 lines
8.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* In-kernel vector facility support functions
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*
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* Copyright IBM Corp. 2015
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* Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
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*/
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#include <linux/kernel.h>
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#include <linux/cpu.h>
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#include <linux/sched.h>
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#include <asm/fpu/types.h>
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#include <asm/fpu/api.h>
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#include <asm/vx-insn.h>
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void __kernel_fpu_begin(struct kernel_fpu *state, u32 flags)
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{
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/*
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* Limit the save to the FPU/vector registers already
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* in use by the previous context
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*/
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flags &= state->mask;
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if (flags & KERNEL_FPC)
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/* Save floating point control */
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asm volatile("stfpc %0" : "=Q" (state->fpc));
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if (!MACHINE_HAS_VX) {
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if (flags & KERNEL_VXR_V0V7) {
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/* Save floating-point registers */
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asm volatile("std 0,%0" : "=Q" (state->fprs[0]));
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asm volatile("std 1,%0" : "=Q" (state->fprs[1]));
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asm volatile("std 2,%0" : "=Q" (state->fprs[2]));
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asm volatile("std 3,%0" : "=Q" (state->fprs[3]));
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asm volatile("std 4,%0" : "=Q" (state->fprs[4]));
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asm volatile("std 5,%0" : "=Q" (state->fprs[5]));
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asm volatile("std 6,%0" : "=Q" (state->fprs[6]));
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asm volatile("std 7,%0" : "=Q" (state->fprs[7]));
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asm volatile("std 8,%0" : "=Q" (state->fprs[8]));
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asm volatile("std 9,%0" : "=Q" (state->fprs[9]));
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asm volatile("std 10,%0" : "=Q" (state->fprs[10]));
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asm volatile("std 11,%0" : "=Q" (state->fprs[11]));
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asm volatile("std 12,%0" : "=Q" (state->fprs[12]));
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asm volatile("std 13,%0" : "=Q" (state->fprs[13]));
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asm volatile("std 14,%0" : "=Q" (state->fprs[14]));
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asm volatile("std 15,%0" : "=Q" (state->fprs[15]));
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}
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return;
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}
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/* Test and save vector registers */
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asm volatile (
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/*
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* Test if any vector register must be saved and, if so,
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* test if all register can be saved.
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*/
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" la 1,%[vxrs]\n" /* load save area */
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" tmll %[m],30\n" /* KERNEL_VXR */
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" jz 7f\n" /* no work -> done */
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" jo 5f\n" /* -> save V0..V31 */
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/*
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* Test for special case KERNEL_FPU_MID only. In this
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* case a vstm V8..V23 is the best instruction
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*/
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" chi %[m],12\n" /* KERNEL_VXR_MID */
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" jne 0f\n" /* -> save V8..V23 */
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" VSTM 8,23,128,1\n" /* vstm %v8,%v23,128(%r1) */
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" j 7f\n"
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/* Test and save the first half of 16 vector registers */
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"0: tmll %[m],6\n" /* KERNEL_VXR_LOW */
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" jz 3f\n" /* -> KERNEL_VXR_HIGH */
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" jo 2f\n" /* 11 -> save V0..V15 */
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" brc 2,1f\n" /* 10 -> save V8..V15 */
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" VSTM 0,7,0,1\n" /* vstm %v0,%v7,0(%r1) */
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" j 3f\n"
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"1: VSTM 8,15,128,1\n" /* vstm %v8,%v15,128(%r1) */
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" j 3f\n"
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"2: VSTM 0,15,0,1\n" /* vstm %v0,%v15,0(%r1) */
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/* Test and save the second half of 16 vector registers */
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"3: tmll %[m],24\n" /* KERNEL_VXR_HIGH */
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" jz 7f\n"
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" jo 6f\n" /* 11 -> save V16..V31 */
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" brc 2,4f\n" /* 10 -> save V24..V31 */
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" VSTM 16,23,256,1\n" /* vstm %v16,%v23,256(%r1) */
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" j 7f\n"
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"4: VSTM 24,31,384,1\n" /* vstm %v24,%v31,384(%r1) */
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" j 7f\n"
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"5: VSTM 0,15,0,1\n" /* vstm %v0,%v15,0(%r1) */
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"6: VSTM 16,31,256,1\n" /* vstm %v16,%v31,256(%r1) */
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"7:"
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: [vxrs] "=Q" (*(struct vx_array *) &state->vxrs)
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: [m] "d" (flags)
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: "1", "cc");
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}
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EXPORT_SYMBOL(__kernel_fpu_begin);
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void __kernel_fpu_end(struct kernel_fpu *state, u32 flags)
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{
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/*
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* Limit the restore to the FPU/vector registers of the
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* previous context that have been overwritte by the
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* current context
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*/
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flags &= state->mask;
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if (flags & KERNEL_FPC)
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/* Restore floating-point controls */
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asm volatile("lfpc %0" : : "Q" (state->fpc));
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if (!MACHINE_HAS_VX) {
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if (flags & KERNEL_VXR_V0V7) {
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/* Restore floating-point registers */
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asm volatile("ld 0,%0" : : "Q" (state->fprs[0]));
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asm volatile("ld 1,%0" : : "Q" (state->fprs[1]));
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asm volatile("ld 2,%0" : : "Q" (state->fprs[2]));
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asm volatile("ld 3,%0" : : "Q" (state->fprs[3]));
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asm volatile("ld 4,%0" : : "Q" (state->fprs[4]));
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asm volatile("ld 5,%0" : : "Q" (state->fprs[5]));
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asm volatile("ld 6,%0" : : "Q" (state->fprs[6]));
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asm volatile("ld 7,%0" : : "Q" (state->fprs[7]));
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asm volatile("ld 8,%0" : : "Q" (state->fprs[8]));
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asm volatile("ld 9,%0" : : "Q" (state->fprs[9]));
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asm volatile("ld 10,%0" : : "Q" (state->fprs[10]));
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asm volatile("ld 11,%0" : : "Q" (state->fprs[11]));
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asm volatile("ld 12,%0" : : "Q" (state->fprs[12]));
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asm volatile("ld 13,%0" : : "Q" (state->fprs[13]));
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asm volatile("ld 14,%0" : : "Q" (state->fprs[14]));
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asm volatile("ld 15,%0" : : "Q" (state->fprs[15]));
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}
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return;
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}
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/* Test and restore (load) vector registers */
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asm volatile (
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/*
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* Test if any vector register must be loaded and, if so,
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* test if all registers can be loaded at once.
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*/
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" la 1,%[vxrs]\n" /* load restore area */
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" tmll %[m],30\n" /* KERNEL_VXR */
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" jz 7f\n" /* no work -> done */
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" jo 5f\n" /* -> restore V0..V31 */
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/*
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* Test for special case KERNEL_FPU_MID only. In this
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* case a vlm V8..V23 is the best instruction
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*/
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" chi %[m],12\n" /* KERNEL_VXR_MID */
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" jne 0f\n" /* -> restore V8..V23 */
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" VLM 8,23,128,1\n" /* vlm %v8,%v23,128(%r1) */
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" j 7f\n"
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/* Test and restore the first half of 16 vector registers */
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"0: tmll %[m],6\n" /* KERNEL_VXR_LOW */
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" jz 3f\n" /* -> KERNEL_VXR_HIGH */
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" jo 2f\n" /* 11 -> restore V0..V15 */
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" brc 2,1f\n" /* 10 -> restore V8..V15 */
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" VLM 0,7,0,1\n" /* vlm %v0,%v7,0(%r1) */
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" j 3f\n"
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"1: VLM 8,15,128,1\n" /* vlm %v8,%v15,128(%r1) */
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" j 3f\n"
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"2: VLM 0,15,0,1\n" /* vlm %v0,%v15,0(%r1) */
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/* Test and restore the second half of 16 vector registers */
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"3: tmll %[m],24\n" /* KERNEL_VXR_HIGH */
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" jz 7f\n"
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" jo 6f\n" /* 11 -> restore V16..V31 */
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" brc 2,4f\n" /* 10 -> restore V24..V31 */
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" VLM 16,23,256,1\n" /* vlm %v16,%v23,256(%r1) */
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" j 7f\n"
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"4: VLM 24,31,384,1\n" /* vlm %v24,%v31,384(%r1) */
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" j 7f\n"
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"5: VLM 0,15,0,1\n" /* vlm %v0,%v15,0(%r1) */
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"6: VLM 16,31,256,1\n" /* vlm %v16,%v31,256(%r1) */
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"7:"
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: [vxrs] "=Q" (*(struct vx_array *) &state->vxrs)
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: [m] "d" (flags)
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: "1", "cc");
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}
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EXPORT_SYMBOL(__kernel_fpu_end);
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void __load_fpu_regs(void)
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{
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struct fpu *state = ¤t->thread.fpu;
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unsigned long *regs = current->thread.fpu.regs;
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asm volatile("lfpc %0" : : "Q" (state->fpc));
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if (likely(MACHINE_HAS_VX)) {
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asm volatile("lgr 1,%0\n"
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"VLM 0,15,0,1\n"
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"VLM 16,31,256,1\n"
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:
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: "d" (regs)
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: "1", "cc", "memory");
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} else {
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asm volatile("ld 0,%0" : : "Q" (regs[0]));
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asm volatile("ld 1,%0" : : "Q" (regs[1]));
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asm volatile("ld 2,%0" : : "Q" (regs[2]));
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asm volatile("ld 3,%0" : : "Q" (regs[3]));
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asm volatile("ld 4,%0" : : "Q" (regs[4]));
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asm volatile("ld 5,%0" : : "Q" (regs[5]));
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asm volatile("ld 6,%0" : : "Q" (regs[6]));
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asm volatile("ld 7,%0" : : "Q" (regs[7]));
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asm volatile("ld 8,%0" : : "Q" (regs[8]));
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asm volatile("ld 9,%0" : : "Q" (regs[9]));
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asm volatile("ld 10,%0" : : "Q" (regs[10]));
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asm volatile("ld 11,%0" : : "Q" (regs[11]));
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asm volatile("ld 12,%0" : : "Q" (regs[12]));
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asm volatile("ld 13,%0" : : "Q" (regs[13]));
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asm volatile("ld 14,%0" : : "Q" (regs[14]));
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asm volatile("ld 15,%0" : : "Q" (regs[15]));
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}
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clear_cpu_flag(CIF_FPU);
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}
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EXPORT_SYMBOL(__load_fpu_regs);
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void load_fpu_regs(void)
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{
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raw_local_irq_disable();
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__load_fpu_regs();
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raw_local_irq_enable();
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}
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EXPORT_SYMBOL(load_fpu_regs);
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void save_fpu_regs(void)
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{
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unsigned long flags, *regs;
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struct fpu *state;
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local_irq_save(flags);
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if (test_cpu_flag(CIF_FPU))
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goto out;
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state = ¤t->thread.fpu;
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regs = current->thread.fpu.regs;
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asm volatile("stfpc %0" : "=Q" (state->fpc));
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if (likely(MACHINE_HAS_VX)) {
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asm volatile("lgr 1,%0\n"
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"VSTM 0,15,0,1\n"
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"VSTM 16,31,256,1\n"
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:
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: "d" (regs)
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: "1", "cc", "memory");
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} else {
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asm volatile("std 0,%0" : "=Q" (regs[0]));
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asm volatile("std 1,%0" : "=Q" (regs[1]));
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asm volatile("std 2,%0" : "=Q" (regs[2]));
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asm volatile("std 3,%0" : "=Q" (regs[3]));
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asm volatile("std 4,%0" : "=Q" (regs[4]));
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asm volatile("std 5,%0" : "=Q" (regs[5]));
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asm volatile("std 6,%0" : "=Q" (regs[6]));
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asm volatile("std 7,%0" : "=Q" (regs[7]));
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asm volatile("std 8,%0" : "=Q" (regs[8]));
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asm volatile("std 9,%0" : "=Q" (regs[9]));
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asm volatile("std 10,%0" : "=Q" (regs[10]));
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asm volatile("std 11,%0" : "=Q" (regs[11]));
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asm volatile("std 12,%0" : "=Q" (regs[12]));
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asm volatile("std 13,%0" : "=Q" (regs[13]));
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asm volatile("std 14,%0" : "=Q" (regs[14]));
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asm volatile("std 15,%0" : "=Q" (regs[15]));
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}
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set_cpu_flag(CIF_FPU);
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out:
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(save_fpu_regs);
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