85 lines
2.4 KiB
C
85 lines
2.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* arch/sh/drivers/pci/fixups-dreamcast.c
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*
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* PCI fixups for the Sega Dreamcast
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*
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* Copyright (C) 2001, 2002 M. R. Brown
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* Copyright (C) 2002, 2003, 2006 Paul Mundt
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*
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* This file originally bore the message (with enclosed-$):
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* Id: pci.c,v 1.3 2003/05/04 19:29:46 lethal Exp
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* Dreamcast PCI: Supports SEGA Broadband Adaptor only.
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*/
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/pci.h>
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#include <linux/dma-map-ops.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <mach/pci.h>
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static void gapspci_fixup_resources(struct pci_dev *dev)
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{
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struct pci_channel *p = dev->sysdata;
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struct resource res;
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struct pci_bus_region region;
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printk(KERN_NOTICE "PCI: Fixing up device %s\n", pci_name(dev));
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switch (dev->device) {
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case PCI_DEVICE_ID_SEGA_BBA:
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/*
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* We also assume that dev->devfn == 0
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*/
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dev->resource[1].start = p->resources[0].start + 0x100;
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dev->resource[1].end = dev->resource[1].start + 0x200 - 1;
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/*
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* This is not a normal BAR, prevent any attempts to move
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* the BAR, as this will result in a bus lock.
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*/
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dev->resource[1].flags |= IORESOURCE_PCI_FIXED;
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/*
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* Redirect dma memory allocations to special memory window.
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*
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* If this GAPSPCI region were mapped by a BAR, the CPU
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* phys_addr_t would be pci_resource_start(), and the bus
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* address would be pci_bus_address(pci_resource_start()).
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* But apparently there's no BAR mapping it, so we just
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* "know" its CPU address is GAPSPCI_DMA_BASE.
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*/
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res.start = GAPSPCI_DMA_BASE;
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res.end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1;
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res.flags = IORESOURCE_MEM;
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pcibios_resource_to_bus(dev->bus, ®ion, &res);
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BUG_ON(dma_declare_coherent_memory(&dev->dev,
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res.start,
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region.start,
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resource_size(&res)));
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break;
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default:
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printk("PCI: Failed resource fixup\n");
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, gapspci_fixup_resources);
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int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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/*
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* The interrupt routing semantics here are quite trivial.
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*
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* We basically only support one interrupt, so we only bother
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* updating a device's interrupt line with this single shared
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* interrupt. Keeps routing quite simple, doesn't it?
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*/
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return GAPSPCI_IRQ;
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}
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