2023-08-30 17:31:07 +02:00
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_SEGMENT_H
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#define _ASM_X86_SEGMENT_H
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#include <linux/const.h>
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#include <asm/alternative.h>
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#include <asm/ibt.h>
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/*
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* Constructor for a conventional segment GDT (or LDT) entry.
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* This is a macro so it can be used in initializers.
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*/
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#define GDT_ENTRY(flags, base, limit) \
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((((base) & _AC(0xff000000,ULL)) << (56-24)) | \
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(((flags) & _AC(0x0000f0ff,ULL)) << 40) | \
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(((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \
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(((base) & _AC(0x00ffffff,ULL)) << 16) | \
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(((limit) & _AC(0x0000ffff,ULL))))
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/* Simple and small GDT entries for booting only: */
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#define GDT_ENTRY_BOOT_CS 2
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#define GDT_ENTRY_BOOT_DS 3
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#define GDT_ENTRY_BOOT_TSS 4
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#define __BOOT_CS (GDT_ENTRY_BOOT_CS*8)
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#define __BOOT_DS (GDT_ENTRY_BOOT_DS*8)
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#define __BOOT_TSS (GDT_ENTRY_BOOT_TSS*8)
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/*
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* Bottom two bits of selector give the ring
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* privilege level
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*/
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#define SEGMENT_RPL_MASK 0x3
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/*
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* When running on Xen PV, the actual privilege level of the kernel is 1,
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* not 0. Testing the Requested Privilege Level in a segment selector to
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* determine whether the context is user mode or kernel mode with
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* SEGMENT_RPL_MASK is wrong because the PV kernel's privilege level
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* matches the 0x3 mask.
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*
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* Testing with USER_SEGMENT_RPL_MASK is valid for both native and Xen PV
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* kernels because privilege level 2 is never used.
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*/
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#define USER_SEGMENT_RPL_MASK 0x2
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/* User mode is privilege level 3: */
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#define USER_RPL 0x3
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/* Bit 2 is Table Indicator (TI): selects between LDT or GDT */
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#define SEGMENT_TI_MASK 0x4
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/* LDT segment has TI set ... */
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#define SEGMENT_LDT 0x4
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/* ... GDT has it cleared */
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#define SEGMENT_GDT 0x0
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#define GDT_ENTRY_INVALID_SEG 0
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2023-10-24 12:59:35 +02:00
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#if defined(CONFIG_X86_32) && !defined(BUILD_VDSO32_64)
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2023-08-30 17:31:07 +02:00
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/*
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* The layout of the per-CPU GDT under Linux:
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*
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* 0 - null <=== cacheline #1
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* 1 - reserved
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* 2 - reserved
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* 3 - reserved
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*
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* 4 - unused <=== cacheline #2
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* 5 - unused
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*
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* ------- start of TLS (Thread-Local Storage) segments:
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*
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* 6 - TLS segment #1 [ glibc's TLS segment ]
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* 7 - TLS segment #2 [ Wine's %fs Win32 segment ]
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* 8 - TLS segment #3 <=== cacheline #3
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* 9 - reserved
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* 10 - reserved
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* 11 - reserved
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*
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* ------- start of kernel segments:
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*
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* 12 - kernel code segment <=== cacheline #4
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* 13 - kernel data segment
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* 14 - default user CS
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* 15 - default user DS
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* 16 - TSS <=== cacheline #5
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* 17 - LDT
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* 18 - PNPBIOS support (16->32 gate)
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* 19 - PNPBIOS support
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* 20 - PNPBIOS support <=== cacheline #6
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* 21 - PNPBIOS support
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* 22 - PNPBIOS support
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* 23 - APM BIOS support
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* 24 - APM BIOS support <=== cacheline #7
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* 25 - APM BIOS support
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*
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* 26 - ESPFIX small SS
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* 27 - per-cpu [ offset to per-cpu data area ]
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* 28 - VDSO getcpu
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* 29 - unused
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* 30 - unused
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* 31 - TSS for double fault handler
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*/
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#define GDT_ENTRY_TLS_MIN 6
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#define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
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#define GDT_ENTRY_KERNEL_CS 12
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#define GDT_ENTRY_KERNEL_DS 13
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#define GDT_ENTRY_DEFAULT_USER_CS 14
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#define GDT_ENTRY_DEFAULT_USER_DS 15
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#define GDT_ENTRY_TSS 16
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#define GDT_ENTRY_LDT 17
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#define GDT_ENTRY_PNPBIOS_CS32 18
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#define GDT_ENTRY_PNPBIOS_CS16 19
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#define GDT_ENTRY_PNPBIOS_DS 20
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#define GDT_ENTRY_PNPBIOS_TS1 21
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#define GDT_ENTRY_PNPBIOS_TS2 22
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#define GDT_ENTRY_APMBIOS_BASE 23
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#define GDT_ENTRY_ESPFIX_SS 26
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#define GDT_ENTRY_PERCPU 27
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#define GDT_ENTRY_CPUNODE 28
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#define GDT_ENTRY_DOUBLEFAULT_TSS 31
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/*
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* Number of entries in the GDT table:
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*/
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#define GDT_ENTRIES 32
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/*
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* Segment selector values corresponding to the above entries:
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*/
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#define __KERNEL_CS (GDT_ENTRY_KERNEL_CS*8)
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#define __KERNEL_DS (GDT_ENTRY_KERNEL_DS*8)
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#define __USER_DS (GDT_ENTRY_DEFAULT_USER_DS*8 + 3)
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#define __USER_CS (GDT_ENTRY_DEFAULT_USER_CS*8 + 3)
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#define __USER32_CS __USER_CS
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#define __ESPFIX_SS (GDT_ENTRY_ESPFIX_SS*8)
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/* segment for calling fn: */
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#define PNP_CS32 (GDT_ENTRY_PNPBIOS_CS32*8)
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/* code segment for BIOS: */
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#define PNP_CS16 (GDT_ENTRY_PNPBIOS_CS16*8)
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/* "Is this PNP code selector (PNP_CS32 or PNP_CS16)?" */
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#define SEGMENT_IS_PNP_CODE(x) (((x) & 0xf4) == PNP_CS32)
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/* data segment for BIOS: */
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#define PNP_DS (GDT_ENTRY_PNPBIOS_DS*8)
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/* transfer data segment: */
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#define PNP_TS1 (GDT_ENTRY_PNPBIOS_TS1*8)
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/* another data segment: */
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#define PNP_TS2 (GDT_ENTRY_PNPBIOS_TS2*8)
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#ifdef CONFIG_SMP
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# define __KERNEL_PERCPU (GDT_ENTRY_PERCPU*8)
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#else
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# define __KERNEL_PERCPU 0
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#endif
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#define __CPUNODE_SEG (GDT_ENTRY_CPUNODE*8 + 3)
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#else /* 64-bit: */
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#include <asm/cache.h>
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#define GDT_ENTRY_KERNEL32_CS 1
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#define GDT_ENTRY_KERNEL_CS 2
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#define GDT_ENTRY_KERNEL_DS 3
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/*
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* We cannot use the same code segment descriptor for user and kernel mode,
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* not even in long flat mode, because of different DPL.
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*
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* GDT layout to get 64-bit SYSCALL/SYSRET support right. SYSRET hardcodes
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* selectors:
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*
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* if returning to 32-bit userspace: cs = STAR.SYSRET_CS,
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* if returning to 64-bit userspace: cs = STAR.SYSRET_CS+16,
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*
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* ss = STAR.SYSRET_CS+8 (in either case)
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*
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* thus USER_DS should be between 32-bit and 64-bit code selectors:
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*/
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#define GDT_ENTRY_DEFAULT_USER32_CS 4
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#define GDT_ENTRY_DEFAULT_USER_DS 5
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#define GDT_ENTRY_DEFAULT_USER_CS 6
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/* Needs two entries */
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#define GDT_ENTRY_TSS 8
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/* Needs two entries */
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#define GDT_ENTRY_LDT 10
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#define GDT_ENTRY_TLS_MIN 12
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#define GDT_ENTRY_TLS_MAX 14
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#define GDT_ENTRY_CPUNODE 15
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/*
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* Number of entries in the GDT table:
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*/
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#define GDT_ENTRIES 16
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/*
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* Segment selector values corresponding to the above entries:
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*
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* Note, selectors also need to have a correct RPL,
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* expressed with the +3 value for user-space selectors:
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*/
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#define __KERNEL32_CS (GDT_ENTRY_KERNEL32_CS*8)
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#define __KERNEL_CS (GDT_ENTRY_KERNEL_CS*8)
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#define __KERNEL_DS (GDT_ENTRY_KERNEL_DS*8)
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#define __USER32_CS (GDT_ENTRY_DEFAULT_USER32_CS*8 + 3)
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#define __USER_DS (GDT_ENTRY_DEFAULT_USER_DS*8 + 3)
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#define __USER_CS (GDT_ENTRY_DEFAULT_USER_CS*8 + 3)
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#define __CPUNODE_SEG (GDT_ENTRY_CPUNODE*8 + 3)
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#endif
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#define IDT_ENTRIES 256
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#define NUM_EXCEPTION_VECTORS 32
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/* Bitmask of exception vectors which push an error code on the stack: */
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#define EXCEPTION_ERRCODE_MASK 0x20027d00
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#define GDT_SIZE (GDT_ENTRIES*8)
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#define GDT_ENTRY_TLS_ENTRIES 3
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#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES* 8)
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/* Bit size and mask of CPU number stored in the per CPU data (and TSC_AUX) */
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#define VDSO_CPUNODE_BITS 12
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#define VDSO_CPUNODE_MASK 0xfff
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#ifndef __ASSEMBLY__
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/* Helper functions to store/load CPU and node numbers */
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static inline unsigned long vdso_encode_cpunode(int cpu, unsigned long node)
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{
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return (node << VDSO_CPUNODE_BITS) | cpu;
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}
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static inline void vdso_read_cpunode(unsigned *cpu, unsigned *node)
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{
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unsigned int p;
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/*
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* Load CPU and node number from the GDT. LSL is faster than RDTSCP
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* and works on all CPUs. This is volatile so that it orders
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* correctly with respect to barrier() and to keep GCC from cleverly
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* hoisting it out of the calling function.
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*
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* If RDPID is available, use it.
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*/
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alternative_io ("lsl %[seg],%[p]",
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".byte 0xf3,0x0f,0xc7,0xf8", /* RDPID %eax/rax */
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X86_FEATURE_RDPID,
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[p] "=a" (p), [seg] "r" (__CPUNODE_SEG));
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if (cpu)
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*cpu = (p & VDSO_CPUNODE_MASK);
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if (node)
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*node = (p >> VDSO_CPUNODE_BITS);
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}
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#endif /* !__ASSEMBLY__ */
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#ifdef __KERNEL__
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/*
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* early_idt_handler_array is an array of entry points referenced in the
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* early IDT. For simplicity, it's a real array with one entry point
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* every nine bytes. That leaves room for an optional 'push $0' if the
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* vector has no error code (two bytes), a 'push $vector_number' (two
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* bytes), and a jump to the common entry code (up to five bytes).
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*/
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#define EARLY_IDT_HANDLER_SIZE (9 + ENDBR_INSN_SIZE)
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/*
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* xen_early_idt_handler_array is for Xen pv guests: for each entry in
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* early_idt_handler_array it contains a prequel in the form of
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* pop %rcx; pop %r11; jmp early_idt_handler_array[i]; summing up to
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* max 8 bytes.
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*/
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#define XEN_EARLY_IDT_HANDLER_SIZE (8 + ENDBR_INSN_SIZE)
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#ifndef __ASSEMBLY__
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extern const char early_idt_handler_array[NUM_EXCEPTION_VECTORS][EARLY_IDT_HANDLER_SIZE];
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extern void early_ignore_irq(void);
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#ifdef CONFIG_XEN_PV
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extern const char xen_early_idt_handler_array[NUM_EXCEPTION_VECTORS][XEN_EARLY_IDT_HANDLER_SIZE];
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#endif
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/*
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* Load a segment. Fall back on loading the zero segment if something goes
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* wrong. This variant assumes that loading zero fully clears the segment.
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* This is always the case on Intel CPUs and, even on 64-bit AMD CPUs, any
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* failure to fully clear the cached descriptor is only observable for
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* FS and GS.
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*/
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#define __loadsegment_simple(seg, value) \
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do { \
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unsigned short __val = (value); \
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\
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asm volatile(" \n" \
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"1: movl %k0,%%" #seg " \n" \
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_ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k0)\
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: "+r" (__val) : : "memory"); \
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} while (0)
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#define __loadsegment_ss(value) __loadsegment_simple(ss, (value))
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#define __loadsegment_ds(value) __loadsegment_simple(ds, (value))
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#define __loadsegment_es(value) __loadsegment_simple(es, (value))
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#ifdef CONFIG_X86_32
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/*
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* On 32-bit systems, the hidden parts of FS and GS are unobservable if
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* the selector is NULL, so there's no funny business here.
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*/
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#define __loadsegment_fs(value) __loadsegment_simple(fs, (value))
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#define __loadsegment_gs(value) __loadsegment_simple(gs, (value))
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#else
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static inline void __loadsegment_fs(unsigned short value)
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{
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asm volatile(" \n"
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"1: movw %0, %%fs \n"
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"2: \n"
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_ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_CLEAR_FS)
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: : "rm" (value) : "memory");
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}
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/* __loadsegment_gs is intentionally undefined. Use load_gs_index instead. */
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#endif
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#define loadsegment(seg, value) __loadsegment_ ## seg (value)
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/*
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* Save a segment register away:
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*/
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#define savesegment(seg, value) \
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asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
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#endif /* !__ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_SEGMENT_H */
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