119 lines
4.8 KiB
C
119 lines
4.8 KiB
C
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_RING_MUX__
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#define __AMDGPU_RING_MUX__
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#include <linux/timer.h>
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#include <linux/spinlock.h>
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#include "amdgpu_ring.h"
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struct amdgpu_ring;
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/**
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* struct amdgpu_mux_entry - the entry recording software rings copying information.
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* @ring: the pointer to the software ring.
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* @start_ptr_in_hw_ring: last start location copied to in the hardware ring.
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* @end_ptr_in_hw_ring: last end location copied to in the hardware ring.
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* @sw_cptr: the position of the copy pointer in the sw ring.
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* @sw_rptr: the read pointer in software ring.
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* @sw_wptr: the write pointer in software ring.
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* @list: list head for amdgpu_mux_chunk
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*/
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struct amdgpu_mux_entry {
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struct amdgpu_ring *ring;
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u64 start_ptr_in_hw_ring;
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u64 end_ptr_in_hw_ring;
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u64 sw_cptr;
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u64 sw_rptr;
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u64 sw_wptr;
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struct list_head list;
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};
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enum amdgpu_ring_mux_offset_type {
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AMDGPU_MUX_OFFSET_TYPE_CONTROL,
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AMDGPU_MUX_OFFSET_TYPE_DE,
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AMDGPU_MUX_OFFSET_TYPE_CE,
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};
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struct amdgpu_ring_mux {
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struct amdgpu_ring *real_ring;
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struct amdgpu_mux_entry *ring_entry;
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unsigned int num_ring_entries;
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unsigned int ring_entry_size;
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/*the lock for copy data from different software rings*/
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spinlock_t lock;
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bool s_resubmit;
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uint32_t seqno_to_resubmit;
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u64 wptr_resubmit;
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struct timer_list resubmit_timer;
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bool pending_trailing_fence_signaled;
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};
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/**
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* struct amdgpu_mux_chunk - save the location of indirect buffer's package on softare rings.
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* @entry: the list entry.
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* @sync_seq: the fence seqno related with the saved IB.
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* @start:- start location on the software ring.
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* @end:- end location on the software ring.
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* @control_offset:- the PRE_RESUME bit position used for resubmission.
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* @de_offset:- the anchor in write_data for de meta of resubmission.
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* @ce_offset:- the anchor in write_data for ce meta of resubmission.
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*/
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struct amdgpu_mux_chunk {
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struct list_head entry;
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uint32_t sync_seq;
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u64 start;
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u64 end;
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u64 cntl_offset;
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u64 de_offset;
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u64 ce_offset;
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};
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int amdgpu_ring_mux_init(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring,
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unsigned int entry_size);
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void amdgpu_ring_mux_fini(struct amdgpu_ring_mux *mux);
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int amdgpu_ring_mux_add_sw_ring(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
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void amdgpu_ring_mux_set_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, u64 wptr);
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u64 amdgpu_ring_mux_get_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
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u64 amdgpu_ring_mux_get_rptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
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void amdgpu_ring_mux_start_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
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void amdgpu_ring_mux_end_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
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void amdgpu_ring_mux_ib_mark_offset(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring,
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u64 offset, enum amdgpu_ring_mux_offset_type type);
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bool amdgpu_mcbp_handle_trailing_fence_irq(struct amdgpu_ring_mux *mux);
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u64 amdgpu_sw_ring_get_rptr_gfx(struct amdgpu_ring *ring);
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u64 amdgpu_sw_ring_get_wptr_gfx(struct amdgpu_ring *ring);
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void amdgpu_sw_ring_set_wptr_gfx(struct amdgpu_ring *ring);
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void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
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void amdgpu_sw_ring_ib_begin(struct amdgpu_ring *ring);
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void amdgpu_sw_ring_ib_end(struct amdgpu_ring *ring);
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void amdgpu_sw_ring_ib_mark_offset(struct amdgpu_ring *ring, enum amdgpu_ring_mux_offset_type type);
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const char *amdgpu_sw_ring_name(int idx);
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unsigned int amdgpu_sw_ring_priority(int idx);
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#endif
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