122 lines
3.6 KiB
C
122 lines
3.6 KiB
C
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "amdgpu_vm.h"
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#include "amdgpu_object.h"
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#include "amdgpu_trace.h"
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/**
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* amdgpu_vm_cpu_map_table - make sure new PDs/PTs are kmapped
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*
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* @table: newly allocated or validated PD/PT
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*/
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static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm *table)
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{
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return amdgpu_bo_kmap(&table->bo, NULL);
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}
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/**
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* amdgpu_vm_cpu_prepare - prepare page table update with the CPU
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*
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* @p: see amdgpu_vm_update_params definition
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* @resv: reservation object with embedded fence
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* @sync_mode: synchronization mode
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*
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* Returns:
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* Negativ errno, 0 for success.
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*/
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static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p,
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struct dma_resv *resv,
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enum amdgpu_sync_mode sync_mode)
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{
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if (!resv)
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return 0;
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return amdgpu_bo_sync_wait_resv(p->adev, resv, sync_mode, p->vm, true);
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}
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/**
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* amdgpu_vm_cpu_update - helper to update page tables via CPU
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*
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* @p: see amdgpu_vm_update_params definition
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* @vmbo: PD/PT to update
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* @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: hw access flags
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*
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* Write count number of PT/PD entries directly.
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*/
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static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p,
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struct amdgpu_bo_vm *vmbo, uint64_t pe,
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uint64_t addr, unsigned count, uint32_t incr,
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uint64_t flags)
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{
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unsigned int i;
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uint64_t value;
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long r;
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r = dma_resv_wait_timeout(vmbo->bo.tbo.base.resv, DMA_RESV_USAGE_KERNEL,
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true, MAX_SCHEDULE_TIMEOUT);
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if (r < 0)
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return r;
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pe += (unsigned long)amdgpu_bo_kptr(&vmbo->bo);
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trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate);
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for (i = 0; i < count; i++) {
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value = p->pages_addr ?
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amdgpu_vm_map_gart(p->pages_addr, addr) :
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addr;
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amdgpu_gmc_set_pte_pde(p->adev, (void *)(uintptr_t)pe,
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i, value, flags);
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addr += incr;
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}
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return 0;
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}
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/**
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* amdgpu_vm_cpu_commit - commit page table update to the HW
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*
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* @p: see amdgpu_vm_update_params definition
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* @fence: unused
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*
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* Make sure that the hardware sees the page table updates.
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*/
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static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p,
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struct dma_fence **fence)
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{
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/* Flush HDP */
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mb();
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amdgpu_device_flush_hdp(p->adev, NULL);
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return 0;
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}
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const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs = {
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.map_table = amdgpu_vm_cpu_map_table,
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.prepare = amdgpu_vm_cpu_prepare,
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.update = amdgpu_vm_cpu_update,
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.commit = amdgpu_vm_cpu_commit
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};
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