96 lines
3.2 KiB
C
96 lines
3.2 KiB
C
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/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_display.h"
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#include "hwmgr.h"
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#include "amdgpu_smu.h"
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#include "amdgpu_dpm_internal.h"
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void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev)
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{
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struct drm_device *ddev = adev_to_drm(adev);
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struct drm_crtc *crtc;
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struct amdgpu_crtc *amdgpu_crtc;
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adev->pm.dpm.new_active_crtcs = 0;
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adev->pm.dpm.new_active_crtc_count = 0;
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if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
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list_for_each_entry(crtc,
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&ddev->mode_config.crtc_list, head) {
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amdgpu_crtc = to_amdgpu_crtc(crtc);
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if (amdgpu_crtc->enabled) {
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adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
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adev->pm.dpm.new_active_crtc_count++;
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}
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}
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}
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}
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u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)
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{
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struct drm_device *dev = adev_to_drm(adev);
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struct drm_crtc *crtc;
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struct amdgpu_crtc *amdgpu_crtc;
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u32 vblank_in_pixels;
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u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
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if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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amdgpu_crtc = to_amdgpu_crtc(crtc);
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if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {
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vblank_in_pixels =
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amdgpu_crtc->hw_mode.crtc_htotal *
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(amdgpu_crtc->hw_mode.crtc_vblank_end -
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amdgpu_crtc->hw_mode.crtc_vdisplay +
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(amdgpu_crtc->v_border * 2));
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vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock;
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break;
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}
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}
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}
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return vblank_time_us;
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}
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u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev)
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{
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struct drm_device *dev = adev_to_drm(adev);
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struct drm_crtc *crtc;
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struct amdgpu_crtc *amdgpu_crtc;
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u32 vrefresh = 0;
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if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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amdgpu_crtc = to_amdgpu_crtc(crtc);
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if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {
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vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
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break;
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}
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}
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}
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return vrefresh;
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}
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