92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "smu7_baco.h"
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#include "tonga_baco.h"
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#include "fiji_baco.h"
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#include "polaris_baco.h"
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#include "ci_baco.h"
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#include "bif/bif_5_0_d.h"
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#include "bif/bif_5_0_sh_mask.h"
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#include "smu/smu_7_1_2_d.h"
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#include "smu/smu_7_1_2_sh_mask.h"
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int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
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uint32_t reg;
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*cap = false;
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if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
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return 0;
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reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
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if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
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*cap = true;
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return 0;
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}
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int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
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uint32_t reg;
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reg = RREG32(mmBACO_CNTL);
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if (reg & BACO_CNTL__BACO_MODE_MASK)
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/* gfx has already entered BACO state */
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*state = BACO_STATE_IN;
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else
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*state = BACO_STATE_OUT;
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return 0;
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}
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int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
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switch (adev->asic_type) {
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case CHIP_TOPAZ:
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case CHIP_TONGA:
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return tonga_baco_set_state(hwmgr, state);
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case CHIP_FIJI:
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return fiji_baco_set_state(hwmgr, state);
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case CHIP_POLARIS10:
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case CHIP_POLARIS11:
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case CHIP_POLARIS12:
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case CHIP_VEGAM:
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return polaris_baco_set_state(hwmgr, state);
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#ifdef CONFIG_DRM_AMDGPU_CIK
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case CHIP_BONAIRE:
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case CHIP_HAWAII:
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return ci_baco_set_state(hwmgr, state);
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#endif
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default:
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return -EINVAL;
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}
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}
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