438 lines
12 KiB
C
438 lines
12 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "smu7_hwmgr.h"
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#include "smu7_clockpowergating.h"
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#include "smu7_common.h"
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static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
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{
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return smum_send_msg_to_smc(hwmgr, enable ?
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PPSMC_MSG_UVDDPM_Enable :
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PPSMC_MSG_UVDDPM_Disable,
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NULL);
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}
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static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
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{
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return smum_send_msg_to_smc(hwmgr, enable ?
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PPSMC_MSG_VCEDPM_Enable :
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PPSMC_MSG_VCEDPM_Disable,
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NULL);
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}
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static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
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{
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if (!bgate)
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smum_update_smc_table(hwmgr, SMU_UVD_TABLE);
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return smu7_enable_disable_uvd_dpm(hwmgr, !bgate);
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}
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static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)
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{
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if (!bgate)
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smum_update_smc_table(hwmgr, SMU_VCE_TABLE);
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return smu7_enable_disable_vce_dpm(hwmgr, !bgate);
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}
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int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
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{
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if (phm_cf_want_uvd_power_gating(hwmgr))
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return smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_UVDPowerOFF,
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NULL);
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return 0;
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}
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static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
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{
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if (phm_cf_want_uvd_power_gating(hwmgr)) {
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_UVDDynamicPowerGating)) {
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return smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_UVDPowerON, 1, NULL);
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} else {
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return smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_UVDPowerON, 0, NULL);
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}
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}
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return 0;
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}
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static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
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{
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if (phm_cf_want_vce_power_gating(hwmgr))
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return smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_VCEPowerOFF,
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NULL);
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return 0;
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}
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static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
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{
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if (phm_cf_want_vce_power_gating(hwmgr))
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return smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_VCEPowerON,
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NULL);
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return 0;
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}
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int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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data->uvd_power_gated = false;
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data->vce_power_gated = false;
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smu7_powerup_uvd(hwmgr);
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smu7_powerup_vce(hwmgr);
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return 0;
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}
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void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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data->uvd_power_gated = bgate;
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if (bgate) {
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amdgpu_device_ip_set_powergating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_PG_STATE_GATE);
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amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_CG_STATE_GATE);
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smu7_update_uvd_dpm(hwmgr, true);
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smu7_powerdown_uvd(hwmgr);
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} else {
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smu7_powerup_uvd(hwmgr);
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amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_CG_STATE_UNGATE);
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amdgpu_device_ip_set_powergating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_PG_STATE_UNGATE);
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smu7_update_uvd_dpm(hwmgr, false);
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}
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}
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void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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data->vce_power_gated = bgate;
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if (bgate) {
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amdgpu_device_ip_set_powergating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_GATE);
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amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_GATE);
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smu7_update_vce_dpm(hwmgr, true);
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smu7_powerdown_vce(hwmgr);
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} else {
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smu7_powerup_vce(hwmgr);
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amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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amdgpu_device_ip_set_powergating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_UNGATE);
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smu7_update_vce_dpm(hwmgr, false);
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}
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}
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int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
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const uint32_t *msg_id)
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{
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PPSMC_Msg msg;
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uint32_t value;
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if (!(hwmgr->feature_mask & PP_ENABLE_GFX_CG_THRU_SMU))
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return 0;
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switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) {
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case PP_GROUP_GFX:
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switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
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case PP_BLOCK_GFX_CG:
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if (PP_STATE_SUPPORT_CG & *msg_id) {
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msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
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PPSMC_MSG_EnableClockGatingFeature :
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PPSMC_MSG_DisableClockGatingFeature;
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value = CG_GFX_CGCG_MASK;
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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if (PP_STATE_SUPPORT_LS & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
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? PPSMC_MSG_EnableClockGatingFeature
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: PPSMC_MSG_DisableClockGatingFeature;
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value = CG_GFX_CGLS_MASK;
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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break;
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case PP_BLOCK_GFX_3D:
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if (PP_STATE_SUPPORT_CG & *msg_id) {
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msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
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PPSMC_MSG_EnableClockGatingFeature :
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PPSMC_MSG_DisableClockGatingFeature;
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value = CG_GFX_3DCG_MASK;
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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if (PP_STATE_SUPPORT_LS & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
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PPSMC_MSG_EnableClockGatingFeature :
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PPSMC_MSG_DisableClockGatingFeature;
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value = CG_GFX_3DLS_MASK;
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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break;
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case PP_BLOCK_GFX_RLC:
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if (PP_STATE_SUPPORT_LS & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
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PPSMC_MSG_EnableClockGatingFeature :
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PPSMC_MSG_DisableClockGatingFeature;
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value = CG_GFX_RLC_LS_MASK;
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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break;
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case PP_BLOCK_GFX_CP:
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if (PP_STATE_SUPPORT_LS & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
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PPSMC_MSG_EnableClockGatingFeature :
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PPSMC_MSG_DisableClockGatingFeature;
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value = CG_GFX_CP_LS_MASK;
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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break;
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case PP_BLOCK_GFX_MG:
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if (PP_STATE_SUPPORT_CG & *msg_id) {
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msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
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PPSMC_MSG_EnableClockGatingFeature :
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PPSMC_MSG_DisableClockGatingFeature;
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value = (CG_CPF_MGCG_MASK | CG_RLC_MGCG_MASK |
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CG_GFX_OTHERS_MGCG_MASK);
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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}
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break;
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case PP_GROUP_SYS:
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switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
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case PP_BLOCK_SYS_BIF:
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if (PP_STATE_SUPPORT_CG & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ?
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PPSMC_MSG_EnableClockGatingFeature :
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PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_BIF_MGCG_MASK;
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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if (PP_STATE_SUPPORT_LS & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
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PPSMC_MSG_EnableClockGatingFeature :
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PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_BIF_MGLS_MASK;
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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break;
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case PP_BLOCK_SYS_MC:
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if (PP_STATE_SUPPORT_CG & *msg_id) {
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msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
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PPSMC_MSG_EnableClockGatingFeature :
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PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_MC_MGCG_MASK;
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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if (PP_STATE_SUPPORT_LS & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
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PPSMC_MSG_EnableClockGatingFeature :
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PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_MC_MGLS_MASK;
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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break;
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case PP_BLOCK_SYS_DRM:
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if (PP_STATE_SUPPORT_CG & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ?
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PPSMC_MSG_EnableClockGatingFeature :
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PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_DRM_MGCG_MASK;
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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if (PP_STATE_SUPPORT_LS & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
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PPSMC_MSG_EnableClockGatingFeature :
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PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_DRM_MGLS_MASK;
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if (smum_send_msg_to_smc_with_parameter(
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hwmgr, msg, value, NULL))
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return -EINVAL;
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}
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break;
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case PP_BLOCK_SYS_HDP:
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if (PP_STATE_SUPPORT_CG & *msg_id) {
|
||
|
|
msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
|
||
|
|
PPSMC_MSG_EnableClockGatingFeature :
|
||
|
|
PPSMC_MSG_DisableClockGatingFeature;
|
||
|
|
value = CG_SYS_HDP_MGCG_MASK;
|
||
|
|
|
||
|
|
if (smum_send_msg_to_smc_with_parameter(
|
||
|
|
hwmgr, msg, value, NULL))
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (PP_STATE_SUPPORT_LS & *msg_id) {
|
||
|
|
msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
|
||
|
|
PPSMC_MSG_EnableClockGatingFeature :
|
||
|
|
PPSMC_MSG_DisableClockGatingFeature;
|
||
|
|
value = CG_SYS_HDP_MGLS_MASK;
|
||
|
|
|
||
|
|
if (smum_send_msg_to_smc_with_parameter(
|
||
|
|
hwmgr, msg, value, NULL))
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PP_BLOCK_SYS_SDMA:
|
||
|
|
if (PP_STATE_SUPPORT_CG & *msg_id) {
|
||
|
|
msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
|
||
|
|
PPSMC_MSG_EnableClockGatingFeature :
|
||
|
|
PPSMC_MSG_DisableClockGatingFeature;
|
||
|
|
value = CG_SYS_SDMA_MGCG_MASK;
|
||
|
|
|
||
|
|
if (smum_send_msg_to_smc_with_parameter(
|
||
|
|
hwmgr, msg, value, NULL))
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (PP_STATE_SUPPORT_LS & *msg_id) {
|
||
|
|
msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
|
||
|
|
PPSMC_MSG_EnableClockGatingFeature :
|
||
|
|
PPSMC_MSG_DisableClockGatingFeature;
|
||
|
|
value = CG_SYS_SDMA_MGLS_MASK;
|
||
|
|
|
||
|
|
if (smum_send_msg_to_smc_with_parameter(
|
||
|
|
hwmgr, msg, value, NULL))
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PP_BLOCK_SYS_ROM:
|
||
|
|
if (PP_STATE_SUPPORT_CG & *msg_id) {
|
||
|
|
msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
|
||
|
|
PPSMC_MSG_EnableClockGatingFeature :
|
||
|
|
PPSMC_MSG_DisableClockGatingFeature;
|
||
|
|
value = CG_SYS_ROM_MASK;
|
||
|
|
|
||
|
|
if (smum_send_msg_to_smc_with_parameter(
|
||
|
|
hwmgr, msg, value, NULL))
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* This function is for Polaris11 only for now,
|
||
|
|
* Powerplay will only control the static per CU Power Gating.
|
||
|
|
* Dynamic per CU Power Gating will be done in gfx.
|
||
|
|
*/
|
||
|
|
int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable)
|
||
|
|
{
|
||
|
|
struct amdgpu_device *adev = hwmgr->adev;
|
||
|
|
|
||
|
|
if (enable)
|
||
|
|
return smum_send_msg_to_smc_with_parameter(hwmgr,
|
||
|
|
PPSMC_MSG_GFX_CU_PG_ENABLE,
|
||
|
|
adev->gfx.cu_info.number,
|
||
|
|
NULL);
|
||
|
|
else
|
||
|
|
return smum_send_msg_to_smc(hwmgr,
|
||
|
|
PPSMC_MSG_GFX_CU_PG_DISABLE,
|
||
|
|
NULL);
|
||
|
|
}
|