320 lines
9.1 KiB
C
320 lines
9.1 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/pci.h>
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#include "smumgr.h"
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#include "smu10_inc.h"
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#include "soc15_common.h"
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#include "smu10_smumgr.h"
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#include "ppatomctrl.h"
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#include "rv_ppsmc.h"
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#include "smu10_driver_if.h"
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#include "smu10.h"
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#include "pp_debug.h"
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#define BUFFER_SIZE 80000
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#define MAX_STRING_SIZE 15
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#define BUFFER_SIZETWO 131072
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#define MP0_Public 0x03800000
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#define MP0_SRAM 0x03900000
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#define MP1_Public 0x03b00000
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#define MP1_SRAM 0x03c00004
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#define smnMP1_FIRMWARE_FLAGS 0x3010028
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static uint32_t smu10_wait_for_response(struct pp_hwmgr *hwmgr)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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uint32_t reg;
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reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
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phm_wait_for_register_unequal(hwmgr, reg,
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0, MP1_C2PMSG_90__CONTENT_MASK);
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return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
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}
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static int smu10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
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uint16_t msg)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
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return 0;
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}
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static uint32_t smu10_read_arg_from_smc(struct pp_hwmgr *hwmgr)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
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}
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static int smu10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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smu10_wait_for_response(hwmgr);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
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smu10_send_msg_to_smc_without_waiting(hwmgr, msg);
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if (smu10_wait_for_response(hwmgr) == 0)
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dev_err(adev->dev, "Failed to send Message %x.\n", msg);
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return 0;
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}
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static int smu10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
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uint16_t msg, uint32_t parameter)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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smu10_wait_for_response(hwmgr);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
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smu10_send_msg_to_smc_without_waiting(hwmgr, msg);
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if (smu10_wait_for_response(hwmgr) == 0)
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dev_err(adev->dev, "Failed to send Message %x.\n", msg);
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return 0;
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}
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static int smu10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id)
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{
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struct smu10_smumgr *priv =
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(struct smu10_smumgr *)(hwmgr->smu_backend);
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struct amdgpu_device *adev = hwmgr->adev;
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PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
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"Invalid SMU Table ID!", return -EINVAL;);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
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"Invalid SMU Table version!", return -EINVAL;);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
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"Invalid SMU Table Length!", return -EINVAL;);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrHigh,
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upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrLow,
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lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_TransferTableSmu2Dram,
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priv->smu_tables.entry[table_id].table_id,
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NULL);
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amdgpu_asic_invalidate_hdp(adev, NULL);
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memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,
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priv->smu_tables.entry[table_id].size);
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return 0;
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}
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static int smu10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id)
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{
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struct smu10_smumgr *priv =
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(struct smu10_smumgr *)(hwmgr->smu_backend);
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struct amdgpu_device *adev = hwmgr->adev;
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PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
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"Invalid SMU Table ID!", return -EINVAL;);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
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"Invalid SMU Table version!", return -EINVAL;);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
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"Invalid SMU Table Length!", return -EINVAL;);
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memcpy(priv->smu_tables.entry[table_id].table, table,
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priv->smu_tables.entry[table_id].size);
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amdgpu_asic_flush_hdp(adev, NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrHigh,
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upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrLow,
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lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_TransferTableDram2Smu,
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priv->smu_tables.entry[table_id].table_id,
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NULL);
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return 0;
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}
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static int smu10_verify_smc_interface(struct pp_hwmgr *hwmgr)
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{
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uint32_t smc_driver_if_version;
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smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetDriverIfVersion,
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&smc_driver_if_version);
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if ((smc_driver_if_version != SMU10_DRIVER_IF_VERSION) &&
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(smc_driver_if_version != SMU10_DRIVER_IF_VERSION + 1)) {
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pr_err("Attempt to read SMC IF Version Number Failed!\n");
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return -EINVAL;
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}
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return 0;
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}
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static int smu10_smu_fini(struct pp_hwmgr *hwmgr)
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{
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struct smu10_smumgr *priv =
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(struct smu10_smumgr *)(hwmgr->smu_backend);
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if (priv) {
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amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
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&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
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&priv->smu_tables.entry[SMU10_WMTABLE].table);
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amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_CLOCKTABLE].handle,
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&priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,
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&priv->smu_tables.entry[SMU10_CLOCKTABLE].table);
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kfree(hwmgr->smu_backend);
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hwmgr->smu_backend = NULL;
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}
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return 0;
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}
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static int smu10_start_smu(struct pp_hwmgr *hwmgr)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion, &hwmgr->smu_version);
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adev->pm.fw_version = hwmgr->smu_version >> 8;
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if (!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
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(adev->apu_flags & AMD_APU_IS_RAVEN) &&
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adev->pm.fw_version < 0x1e45)
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adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
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if (smu10_verify_smc_interface(hwmgr))
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return -EINVAL;
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return 0;
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}
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static int smu10_smu_init(struct pp_hwmgr *hwmgr)
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{
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struct smu10_smumgr *priv;
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int r;
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priv = kzalloc(sizeof(struct smu10_smumgr), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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hwmgr->smu_backend = priv;
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/* allocate space for watermarks table */
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r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
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sizeof(Watermarks_t), PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT,
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&priv->smu_tables.entry[SMU10_WMTABLE].handle,
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&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
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&priv->smu_tables.entry[SMU10_WMTABLE].table);
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if (r)
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goto err0;
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priv->smu_tables.entry[SMU10_WMTABLE].version = 0x01;
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priv->smu_tables.entry[SMU10_WMTABLE].size = sizeof(Watermarks_t);
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priv->smu_tables.entry[SMU10_WMTABLE].table_id = TABLE_WATERMARKS;
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/* allocate space for watermarks table */
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r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
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sizeof(DpmClocks_t), PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT,
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&priv->smu_tables.entry[SMU10_CLOCKTABLE].handle,
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&priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,
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&priv->smu_tables.entry[SMU10_CLOCKTABLE].table);
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if (r)
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goto err1;
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priv->smu_tables.entry[SMU10_CLOCKTABLE].version = 0x01;
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priv->smu_tables.entry[SMU10_CLOCKTABLE].size = sizeof(DpmClocks_t);
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priv->smu_tables.entry[SMU10_CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
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return 0;
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err1:
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amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
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&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
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&priv->smu_tables.entry[SMU10_WMTABLE].table);
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err0:
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kfree(priv);
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return -EINVAL;
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}
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static int smu10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)
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{
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int ret;
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if (rw)
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ret = smu10_copy_table_from_smc(hwmgr, table, table_id);
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else
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ret = smu10_copy_table_to_smc(hwmgr, table, table_id);
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return ret;
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}
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const struct pp_smumgr_func smu10_smu_funcs = {
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.name = "smu10_smu",
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.smu_init = &smu10_smu_init,
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.smu_fini = &smu10_smu_fini,
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.start_smu = &smu10_start_smu,
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.request_smu_load_specific_fw = NULL,
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.send_msg_to_smc = &smu10_send_msg_to_smc,
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.send_msg_to_smc_with_parameter = &smu10_send_msg_to_smc_with_parameter,
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.download_pptable_settings = NULL,
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.upload_pptable_settings = NULL,
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.get_argument = smu10_read_arg_from_smc,
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.smc_table_manager = smu10_smc_table_manager,
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};
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