396 lines
12 KiB
C
396 lines
12 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/pci.h>
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#include "smumgr.h"
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#include "vega10_inc.h"
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#include "soc15_common.h"
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#include "vega10_smumgr.h"
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#include "vega10_hwmgr.h"
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#include "vega10_ppsmc.h"
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#include "smu9_driver_if.h"
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#include "smu9_smumgr.h"
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#include "ppatomctrl.h"
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#include "pp_debug.h"
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static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id)
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{
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struct vega10_smumgr *priv = hwmgr->smu_backend;
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struct amdgpu_device *adev = hwmgr->adev;
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PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
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"Invalid SMU Table ID!", return -EINVAL);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
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"Invalid SMU Table version!", return -EINVAL);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
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"Invalid SMU Table Length!", return -EINVAL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrHigh,
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upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrLow,
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lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_TransferTableSmu2Dram,
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priv->smu_tables.entry[table_id].table_id,
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NULL);
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amdgpu_asic_invalidate_hdp(adev, NULL);
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memcpy(table, priv->smu_tables.entry[table_id].table,
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priv->smu_tables.entry[table_id].size);
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return 0;
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}
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static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id)
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{
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struct vega10_smumgr *priv = hwmgr->smu_backend;
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struct amdgpu_device *adev = hwmgr->adev;
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/* under sriov, vbios or hypervisor driver
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* has already copy table to smc so here only skip it
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*/
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if (!hwmgr->not_vf)
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return 0;
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PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
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"Invalid SMU Table ID!", return -EINVAL);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
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"Invalid SMU Table version!", return -EINVAL);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
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"Invalid SMU Table Length!", return -EINVAL);
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memcpy(priv->smu_tables.entry[table_id].table, table,
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priv->smu_tables.entry[table_id].size);
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amdgpu_asic_flush_hdp(adev, NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrHigh,
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upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrLow,
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lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_TransferTableDram2Smu,
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priv->smu_tables.entry[table_id].table_id,
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NULL);
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return 0;
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}
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int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
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bool enable, uint32_t feature_mask)
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{
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int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
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PPSMC_MSG_DisableSmuFeatures;
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/* VF has no permission to change smu feature due
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* to security concern even under pp one vf mode
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* it still can't do it. For vega10, the smu in
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* vbios will enable the appropriate features.
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* */
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if (!hwmgr->not_vf)
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return 0;
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return smum_send_msg_to_smc_with_parameter(hwmgr,
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msg, feature_mask, NULL);
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}
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int vega10_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
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uint64_t *features_enabled)
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{
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uint32_t enabled_features;
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if (features_enabled == NULL)
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return -EINVAL;
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smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetEnabledSmuFeatures,
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&enabled_features);
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*features_enabled = enabled_features;
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return 0;
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}
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static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr)
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{
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uint64_t features_enabled = 0;
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vega10_get_enabled_smc_features(hwmgr, &features_enabled);
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if (features_enabled & SMC_DPM_FEATURES)
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return true;
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else
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return false;
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}
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static int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
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{
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struct vega10_smumgr *priv = hwmgr->smu_backend;
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if (priv->smu_tables.entry[TOOLSTABLE].mc_addr) {
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetToolsDramAddrHigh,
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upper_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr),
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetToolsDramAddrLow,
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lower_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr),
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NULL);
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}
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return 0;
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}
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static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr)
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{
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uint32_t smc_driver_if_version;
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struct amdgpu_device *adev = hwmgr->adev;
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uint32_t dev_id;
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uint32_t rev_id;
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetDriverIfVersion,
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&smc_driver_if_version),
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"Attempt to get SMC IF Version Number Failed!",
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return -EINVAL);
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dev_id = adev->pdev->device;
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rev_id = adev->pdev->revision;
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if (!((dev_id == 0x687f) &&
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((rev_id == 0xc0) ||
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(rev_id == 0xc1) ||
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(rev_id == 0xc3)))) {
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if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) {
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pr_err("Your firmware(0x%x) doesn't match SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware!\n",
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smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
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return -EINVAL;
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}
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}
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return 0;
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}
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static int vega10_smu_init(struct pp_hwmgr *hwmgr)
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{
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struct vega10_smumgr *priv;
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unsigned long tools_size;
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int ret;
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struct cgs_firmware_info info = {0};
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ret = cgs_get_firmware_info(hwmgr->device,
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CGS_UCODE_ID_SMU,
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&info);
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if (ret || !info.kptr)
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return -EINVAL;
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priv = kzalloc(sizeof(struct vega10_smumgr), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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hwmgr->smu_backend = priv;
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/* allocate space for pptable */
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ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
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sizeof(PPTable_t),
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PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&priv->smu_tables.entry[PPTABLE].handle,
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&priv->smu_tables.entry[PPTABLE].mc_addr,
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&priv->smu_tables.entry[PPTABLE].table);
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if (ret)
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goto free_backend;
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priv->smu_tables.entry[PPTABLE].version = 0x01;
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priv->smu_tables.entry[PPTABLE].size = sizeof(PPTable_t);
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priv->smu_tables.entry[PPTABLE].table_id = TABLE_PPTABLE;
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/* allocate space for watermarks table */
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ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
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sizeof(Watermarks_t),
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PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&priv->smu_tables.entry[WMTABLE].handle,
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&priv->smu_tables.entry[WMTABLE].mc_addr,
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&priv->smu_tables.entry[WMTABLE].table);
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if (ret)
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goto err0;
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priv->smu_tables.entry[WMTABLE].version = 0x01;
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priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t);
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priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
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/* allocate space for AVFS table */
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ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
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sizeof(AvfsTable_t),
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PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&priv->smu_tables.entry[AVFSTABLE].handle,
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&priv->smu_tables.entry[AVFSTABLE].mc_addr,
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&priv->smu_tables.entry[AVFSTABLE].table);
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if (ret)
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goto err1;
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priv->smu_tables.entry[AVFSTABLE].version = 0x01;
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priv->smu_tables.entry[AVFSTABLE].size = sizeof(AvfsTable_t);
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priv->smu_tables.entry[AVFSTABLE].table_id = TABLE_AVFS;
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tools_size = 0x19000;
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if (tools_size) {
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ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
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tools_size,
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PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&priv->smu_tables.entry[TOOLSTABLE].handle,
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&priv->smu_tables.entry[TOOLSTABLE].mc_addr,
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&priv->smu_tables.entry[TOOLSTABLE].table);
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if (ret)
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goto err2;
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priv->smu_tables.entry[TOOLSTABLE].version = 0x01;
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priv->smu_tables.entry[TOOLSTABLE].size = tools_size;
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priv->smu_tables.entry[TOOLSTABLE].table_id = TABLE_PMSTATUSLOG;
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}
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/* allocate space for AVFS Fuse table */
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ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
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sizeof(AvfsFuseOverride_t),
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PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&priv->smu_tables.entry[AVFSFUSETABLE].handle,
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&priv->smu_tables.entry[AVFSFUSETABLE].mc_addr,
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&priv->smu_tables.entry[AVFSFUSETABLE].table);
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if (ret)
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goto err3;
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priv->smu_tables.entry[AVFSFUSETABLE].version = 0x01;
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priv->smu_tables.entry[AVFSFUSETABLE].size = sizeof(AvfsFuseOverride_t);
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priv->smu_tables.entry[AVFSFUSETABLE].table_id = TABLE_AVFS_FUSE_OVERRIDE;
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return 0;
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err3:
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if (priv->smu_tables.entry[TOOLSTABLE].table)
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amdgpu_bo_free_kernel(&priv->smu_tables.entry[TOOLSTABLE].handle,
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&priv->smu_tables.entry[TOOLSTABLE].mc_addr,
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&priv->smu_tables.entry[TOOLSTABLE].table);
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err2:
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amdgpu_bo_free_kernel(&priv->smu_tables.entry[AVFSTABLE].handle,
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&priv->smu_tables.entry[AVFSTABLE].mc_addr,
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&priv->smu_tables.entry[AVFSTABLE].table);
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err1:
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amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle,
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&priv->smu_tables.entry[WMTABLE].mc_addr,
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&priv->smu_tables.entry[WMTABLE].table);
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err0:
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amdgpu_bo_free_kernel(&priv->smu_tables.entry[PPTABLE].handle,
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&priv->smu_tables.entry[PPTABLE].mc_addr,
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&priv->smu_tables.entry[PPTABLE].table);
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free_backend:
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kfree(hwmgr->smu_backend);
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return -EINVAL;
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}
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static int vega10_smu_fini(struct pp_hwmgr *hwmgr)
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{
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struct vega10_smumgr *priv = hwmgr->smu_backend;
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if (priv) {
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amdgpu_bo_free_kernel(&priv->smu_tables.entry[PPTABLE].handle,
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&priv->smu_tables.entry[PPTABLE].mc_addr,
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&priv->smu_tables.entry[PPTABLE].table);
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amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle,
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&priv->smu_tables.entry[WMTABLE].mc_addr,
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&priv->smu_tables.entry[WMTABLE].table);
|
||
|
|
amdgpu_bo_free_kernel(&priv->smu_tables.entry[AVFSTABLE].handle,
|
||
|
|
&priv->smu_tables.entry[AVFSTABLE].mc_addr,
|
||
|
|
&priv->smu_tables.entry[AVFSTABLE].table);
|
||
|
|
if (priv->smu_tables.entry[TOOLSTABLE].table)
|
||
|
|
amdgpu_bo_free_kernel(&priv->smu_tables.entry[TOOLSTABLE].handle,
|
||
|
|
&priv->smu_tables.entry[TOOLSTABLE].mc_addr,
|
||
|
|
&priv->smu_tables.entry[TOOLSTABLE].table);
|
||
|
|
amdgpu_bo_free_kernel(&priv->smu_tables.entry[AVFSFUSETABLE].handle,
|
||
|
|
&priv->smu_tables.entry[AVFSFUSETABLE].mc_addr,
|
||
|
|
&priv->smu_tables.entry[AVFSFUSETABLE].table);
|
||
|
|
kfree(hwmgr->smu_backend);
|
||
|
|
hwmgr->smu_backend = NULL;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int vega10_start_smu(struct pp_hwmgr *hwmgr)
|
||
|
|
{
|
||
|
|
if (!smu9_is_smc_ram_running(hwmgr))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr),
|
||
|
|
"Failed to verify SMC interface!",
|
||
|
|
return -EINVAL);
|
||
|
|
|
||
|
|
vega10_set_tools_address(hwmgr);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int vega10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,
|
||
|
|
uint16_t table_id, bool rw)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (rw)
|
||
|
|
ret = vega10_copy_table_from_smc(hwmgr, table, table_id);
|
||
|
|
else
|
||
|
|
ret = vega10_copy_table_to_smc(hwmgr, table, table_id);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct pp_smumgr_func vega10_smu_funcs = {
|
||
|
|
.name = "vega10_smu",
|
||
|
|
.smu_init = &vega10_smu_init,
|
||
|
|
.smu_fini = &vega10_smu_fini,
|
||
|
|
.start_smu = &vega10_start_smu,
|
||
|
|
.request_smu_load_specific_fw = NULL,
|
||
|
|
.send_msg_to_smc = &smu9_send_msg_to_smc,
|
||
|
|
.send_msg_to_smc_with_parameter = &smu9_send_msg_to_smc_with_parameter,
|
||
|
|
.download_pptable_settings = NULL,
|
||
|
|
.upload_pptable_settings = NULL,
|
||
|
|
.is_dpm_running = vega10_is_dpm_running,
|
||
|
|
.get_argument = smu9_get_argument,
|
||
|
|
.smc_table_manager = vega10_smc_table_manager,
|
||
|
|
};
|