152 lines
7.1 KiB
C
152 lines
7.1 KiB
C
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_AUDIO_REGS_H__
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#define __INTEL_AUDIO_REGS_H__
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#include "intel_display_reg_defs.h"
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#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
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#define G4X_ELD_VALID REG_BIT(14)
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#define G4X_ELD_BUFFER_SIZE_MASK REG_GENMASK(13, 9)
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#define G4X_ELD_ADDRESS_MASK REG_GENMASK(8, 5)
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#define G4X_ELD_ACK REG_BIT(4)
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#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
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#define _IBX_HDMIW_HDMIEDID_A 0xE2050
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#define _IBX_HDMIW_HDMIEDID_B 0xE2150
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#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
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_IBX_HDMIW_HDMIEDID_B)
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#define _IBX_AUD_CNTL_ST_A 0xE20B4
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#define _IBX_AUD_CNTL_ST_B 0xE21B4
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#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
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_IBX_AUD_CNTL_ST_B)
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#define IBX_ELD_BUFFER_SIZE_MASK REG_GENMASK(14, 10)
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#define IBX_ELD_ADDRESS_MASK REG_GENMASK(9, 5)
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#define IBX_ELD_ACK REG_BIT(4)
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#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
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#define IBX_CP_READY(port) REG_BIT(((port) - 1) * 4 + 1)
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#define IBX_ELD_VALID(port) REG_BIT(((port) - 1) * 4 + 0)
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#define _CPT_HDMIW_HDMIEDID_A 0xE5050
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#define _CPT_HDMIW_HDMIEDID_B 0xE5150
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#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
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#define _CPT_AUD_CNTL_ST_A 0xE50B4
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#define _CPT_AUD_CNTL_ST_B 0xE51B4
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#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
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#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
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#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
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#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
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#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
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#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
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#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
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#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
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#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
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#define _IBX_AUD_CONFIG_A 0xe2000
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#define _IBX_AUD_CONFIG_B 0xe2100
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#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
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#define _CPT_AUD_CONFIG_A 0xe5000
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#define _CPT_AUD_CONFIG_B 0xe5100
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#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
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#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
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#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
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#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
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#define AUD_CONFIG_N_VALUE_INDEX REG_BIT(29)
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#define AUD_CONFIG_N_PROG_ENABLE REG_BIT(28)
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#define AUD_CONFIG_UPPER_N_MASK REG_GENMASK(27, 20)
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#define AUD_CONFIG_LOWER_N_MASK REG_GENMASK(15, 4)
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#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | \
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AUD_CONFIG_LOWER_N_MASK)
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#define AUD_CONFIG_N(n) (REG_FIELD_PREP(AUD_CONFIG_UPPER_N_MASK, (n) >> 12) | \
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REG_FIELD_PREP(AUD_CONFIG_LOWER_N_MASK, (n) & 0xfff))
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK REG_GENMASK(19, 16)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 0)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 1)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 2)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 3)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 4)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 5)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 6)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 7)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 8)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 9)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 10)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 11)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 12)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 13)
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#define AUD_CONFIG_DISABLE_NCTS REG_BIT(3)
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#define _HSW_AUD_CONFIG_A 0x65000
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#define _HSW_AUD_CONFIG_B 0x65100
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#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
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#define _HSW_AUD_MISC_CTRL_A 0x65010
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#define _HSW_AUD_MISC_CTRL_B 0x65110
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#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
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#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
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#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
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#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
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#define AUD_M_CTS_M_VALUE_INDEX REG_BIT(21)
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#define AUD_M_CTS_M_PROG_ENABLE REG_BIT(20)
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#define AUD_CONFIG_M_MASK REG_GENMASK(19, 0)
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#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
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#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
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#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
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/* Audio Digital Converter */
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#define _HSW_AUD_DIG_CNVT_1 0x65080
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#define _HSW_AUD_DIG_CNVT_2 0x65180
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#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
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#define DIP_PORT_SEL_MASK 0x3
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#define _HSW_AUD_EDID_DATA_A 0x65050
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#define _HSW_AUD_EDID_DATA_B 0x65150
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#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
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#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
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#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
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#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
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#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
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#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
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#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
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#define _AUD_TCA_DP_2DOT0_CTRL 0x650bc
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#define _AUD_TCB_DP_2DOT0_CTRL 0x651bc
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#define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL)
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#define AUD_ENABLE_SDP_SPLIT REG_BIT(31)
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#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
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#define SKL_AUD_CODEC_WAKE_SIGNAL REG_BIT(15)
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#define AUD_FREQ_CNTRL _MMIO(0x65900)
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#define AUD_PIN_BUF_CTL _MMIO(0x48414)
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#define AUD_PIN_BUF_ENABLE REG_BIT(31)
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#define AUD_TS_CDCLK_M _MMIO(0x65ea0)
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#define AUD_TS_CDCLK_M_EN REG_BIT(31)
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#define AUD_TS_CDCLK_N _MMIO(0x65ea4)
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/* Display Audio Config Reg */
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#define AUD_CONFIG_BE _MMIO(0x65ef0)
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#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
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#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))
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#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))
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#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))
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#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))
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#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))
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#define HBLANK_START_COUNT_8 0
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#define HBLANK_START_COUNT_16 1
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#define HBLANK_START_COUNT_32 2
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#define HBLANK_START_COUNT_64 3
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#define HBLANK_START_COUNT_96 4
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#define HBLANK_START_COUNT_128 5
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#endif /* __INTEL_AUDIO_REGS_H__ */
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