130 lines
4.2 KiB
C
130 lines
4.2 KiB
C
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __INTEL_DISPLAY_DEVICE_H__
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#define __INTEL_DISPLAY_DEVICE_H__
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#include <linux/types.h>
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#include "intel_display_limits.h"
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struct drm_i915_private;
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#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
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/* Keep in alphabetical order */ \
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func(cursor_needs_physical); \
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func(has_cdclk_crawl); \
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func(has_cdclk_squash); \
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func(has_ddi); \
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func(has_dp_mst); \
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func(has_dsb); \
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func(has_fpga_dbg); \
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func(has_gmch); \
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func(has_hotplug); \
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func(has_hti); \
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func(has_ipc); \
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func(has_overlay); \
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func(has_psr); \
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func(has_psr_hw_tracking); \
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func(overlay_needs_physical); \
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func(supports_tv);
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#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
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#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
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#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
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#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
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#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))
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#define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
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#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
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#define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc)
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#define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
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#define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst)
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#define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
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#define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
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#define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
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#define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
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#define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
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#define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
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#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
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#define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
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#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))
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#define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
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#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
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#define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
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#define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
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#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
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#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
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#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
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#define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay)
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#define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr)
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#define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking)
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#define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
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#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
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#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
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BIT(trans)) != 0)
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#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
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#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
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#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
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#define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
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#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
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struct intel_display_runtime_info {
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struct {
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u16 ver;
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u16 rel;
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u16 step;
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} ip;
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u8 pipe_mask;
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u8 cpu_transcoder_mask;
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u8 num_sprites[I915_MAX_PIPES];
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u8 num_scalers[I915_MAX_PIPES];
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u8 fbc_mask;
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bool has_hdcp;
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bool has_dmc;
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bool has_dsc;
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};
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struct intel_display_device_info {
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/* Initial runtime info. */
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const struct intel_display_runtime_info __runtime_defaults;
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u8 abox_mask;
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struct {
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u16 size; /* in blocks */
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u8 slice_mask;
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} dbuf;
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#define DEFINE_FLAG(name) u8 name:1
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DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
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#undef DEFINE_FLAG
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/* Global register offset for the display engine */
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u32 mmio_offset;
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/* Register offsets for the various display pipes and transcoders */
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u32 pipe_offsets[I915_MAX_TRANSCODERS];
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u32 trans_offsets[I915_MAX_TRANSCODERS];
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u32 cursor_offsets[I915_MAX_PIPES];
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struct {
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u32 degamma_lut_size;
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u32 gamma_lut_size;
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u32 degamma_lut_tests;
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u32 gamma_lut_tests;
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} color;
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};
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const struct intel_display_device_info *
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intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
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u16 *ver, u16 *rel, u16 *step);
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void intel_display_device_info_runtime_init(struct drm_i915_private *i915);
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#endif
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