409 lines
10 KiB
C
409 lines
10 KiB
C
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i9xx_wm.h"
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#include "intel_display_types.h"
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#include "intel_wm.h"
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#include "skl_watermark.h"
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/**
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* intel_update_watermarks - update FIFO watermark values based on current modes
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* @i915: i915 device
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*
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* Calculate watermark values for the various WM regs based on current mode
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* and plane configuration.
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*
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* There are several cases to deal with here:
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* - normal (i.e. non-self-refresh)
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* - self-refresh (SR) mode
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* - lines are large relative to FIFO size (buffer can hold up to 2)
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* - lines are small relative to FIFO size (buffer can hold more than 2
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* lines), so need to account for TLB latency
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*
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* The normal calculation is:
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* watermark = dotclock * bytes per pixel * latency
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* where latency is platform & configuration dependent (we assume pessimal
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* values here).
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*
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* The SR calculation is:
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* watermark = (trunc(latency/line time)+1) * surface width *
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* bytes per pixel
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* where
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* line time = htotal / dotclock
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* surface width = hdisplay for normal plane and 64 for cursor
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* and latency is assumed to be high, as above.
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*
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* The final value programmed to the register should always be rounded up,
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* and include an extra 2 entries to account for clock crossings.
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*
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* We don't use the sprite, so we can ignore that. And on Crestline we have
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* to set the non-SR watermarks to 8.
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*/
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void intel_update_watermarks(struct drm_i915_private *i915)
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{
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if (i915->display.funcs.wm->update_wm)
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i915->display.funcs.wm->update_wm(i915);
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}
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int intel_compute_pipe_wm(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *i915 = to_i915(state->base.dev);
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if (i915->display.funcs.wm->compute_pipe_wm)
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return i915->display.funcs.wm->compute_pipe_wm(state, crtc);
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return 0;
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}
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int intel_compute_intermediate_wm(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *i915 = to_i915(state->base.dev);
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if (!i915->display.funcs.wm->compute_intermediate_wm)
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return 0;
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if (drm_WARN_ON(&i915->drm, !i915->display.funcs.wm->compute_pipe_wm))
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return 0;
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return i915->display.funcs.wm->compute_intermediate_wm(state, crtc);
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}
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bool intel_initial_watermarks(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *i915 = to_i915(state->base.dev);
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if (i915->display.funcs.wm->initial_watermarks) {
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i915->display.funcs.wm->initial_watermarks(state, crtc);
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return true;
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}
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return false;
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}
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void intel_atomic_update_watermarks(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *i915 = to_i915(state->base.dev);
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if (i915->display.funcs.wm->atomic_update_watermarks)
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i915->display.funcs.wm->atomic_update_watermarks(state, crtc);
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}
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void intel_optimize_watermarks(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *i915 = to_i915(state->base.dev);
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if (i915->display.funcs.wm->optimize_watermarks)
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i915->display.funcs.wm->optimize_watermarks(state, crtc);
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}
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int intel_compute_global_watermarks(struct intel_atomic_state *state)
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{
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struct drm_i915_private *i915 = to_i915(state->base.dev);
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if (i915->display.funcs.wm->compute_global_watermarks)
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return i915->display.funcs.wm->compute_global_watermarks(state);
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return 0;
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}
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void intel_wm_get_hw_state(struct drm_i915_private *i915)
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{
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if (i915->display.funcs.wm->get_hw_state)
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return i915->display.funcs.wm->get_hw_state(i915);
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}
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bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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{
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struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
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/* FIXME check the 'enable' instead */
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if (!crtc_state->hw.active)
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return false;
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/*
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* Treat cursor with fb as always visible since cursor updates
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* can happen faster than the vrefresh rate, and the current
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* watermark code doesn't handle that correctly. Cursor updates
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* which set/clear the fb or change the cursor size are going
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* to get throttled by intel_legacy_cursor_update() to work
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* around this problem with the watermark code.
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*/
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if (plane->id == PLANE_CURSOR)
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return plane_state->hw.fb != NULL;
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else
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return plane_state->uapi.visible;
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}
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void intel_print_wm_latency(struct drm_i915_private *dev_priv,
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const char *name, const u16 wm[])
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{
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int level;
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for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
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unsigned int latency = wm[level];
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if (latency == 0) {
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drm_dbg_kms(&dev_priv->drm,
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"%s WM%d latency not provided\n",
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name, level);
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continue;
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}
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/*
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* - latencies are in us on gen9.
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* - before then, WM1+ latency values are in 0.5us units
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*/
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if (DISPLAY_VER(dev_priv) >= 9)
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latency *= 10;
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else if (level > 0)
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latency *= 5;
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drm_dbg_kms(&dev_priv->drm,
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"%s WM%d latency %u (%u.%u usec)\n", name, level,
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wm[level], latency / 10, latency % 10);
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}
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}
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void intel_wm_init(struct drm_i915_private *i915)
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{
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if (DISPLAY_VER(i915) >= 9)
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skl_wm_init(i915);
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else
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i9xx_wm_init(i915);
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}
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static void wm_latency_show(struct seq_file *m, const u16 wm[8])
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{
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struct drm_i915_private *dev_priv = m->private;
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int level;
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drm_modeset_lock_all(&dev_priv->drm);
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for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
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unsigned int latency = wm[level];
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/*
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* - WM1+ latency values in 0.5us units
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* - latencies are in us on gen9/vlv/chv
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*/
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if (DISPLAY_VER(dev_priv) >= 9 ||
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IS_VALLEYVIEW(dev_priv) ||
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IS_CHERRYVIEW(dev_priv) ||
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IS_G4X(dev_priv))
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latency *= 10;
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else if (level > 0)
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latency *= 5;
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seq_printf(m, "WM%d %u (%u.%u usec)\n",
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level, wm[level], latency / 10, latency % 10);
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}
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drm_modeset_unlock_all(&dev_priv->drm);
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}
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static int pri_wm_latency_show(struct seq_file *m, void *data)
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{
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struct drm_i915_private *dev_priv = m->private;
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const u16 *latencies;
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if (DISPLAY_VER(dev_priv) >= 9)
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latencies = dev_priv->display.wm.skl_latency;
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else
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latencies = dev_priv->display.wm.pri_latency;
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wm_latency_show(m, latencies);
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return 0;
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}
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static int spr_wm_latency_show(struct seq_file *m, void *data)
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{
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struct drm_i915_private *dev_priv = m->private;
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const u16 *latencies;
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if (DISPLAY_VER(dev_priv) >= 9)
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latencies = dev_priv->display.wm.skl_latency;
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else
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latencies = dev_priv->display.wm.spr_latency;
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wm_latency_show(m, latencies);
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return 0;
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}
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static int cur_wm_latency_show(struct seq_file *m, void *data)
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{
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struct drm_i915_private *dev_priv = m->private;
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const u16 *latencies;
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if (DISPLAY_VER(dev_priv) >= 9)
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latencies = dev_priv->display.wm.skl_latency;
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else
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latencies = dev_priv->display.wm.cur_latency;
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wm_latency_show(m, latencies);
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return 0;
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}
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static int pri_wm_latency_open(struct inode *inode, struct file *file)
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{
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struct drm_i915_private *dev_priv = inode->i_private;
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if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
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return -ENODEV;
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return single_open(file, pri_wm_latency_show, dev_priv);
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}
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static int spr_wm_latency_open(struct inode *inode, struct file *file)
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{
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struct drm_i915_private *dev_priv = inode->i_private;
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if (HAS_GMCH(dev_priv))
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return -ENODEV;
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return single_open(file, spr_wm_latency_show, dev_priv);
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}
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static int cur_wm_latency_open(struct inode *inode, struct file *file)
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{
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struct drm_i915_private *dev_priv = inode->i_private;
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if (HAS_GMCH(dev_priv))
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return -ENODEV;
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return single_open(file, cur_wm_latency_show, dev_priv);
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}
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static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
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size_t len, loff_t *offp, u16 wm[8])
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{
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struct seq_file *m = file->private_data;
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struct drm_i915_private *dev_priv = m->private;
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u16 new[8] = { 0 };
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int level;
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int ret;
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char tmp[32];
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if (len >= sizeof(tmp))
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return -EINVAL;
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if (copy_from_user(tmp, ubuf, len))
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return -EFAULT;
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tmp[len] = '\0';
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ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
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&new[0], &new[1], &new[2], &new[3],
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&new[4], &new[5], &new[6], &new[7]);
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if (ret != dev_priv->display.wm.num_levels)
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return -EINVAL;
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drm_modeset_lock_all(&dev_priv->drm);
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for (level = 0; level < dev_priv->display.wm.num_levels; level++)
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wm[level] = new[level];
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drm_modeset_unlock_all(&dev_priv->drm);
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return len;
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}
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static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
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size_t len, loff_t *offp)
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{
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struct seq_file *m = file->private_data;
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struct drm_i915_private *dev_priv = m->private;
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u16 *latencies;
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if (DISPLAY_VER(dev_priv) >= 9)
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latencies = dev_priv->display.wm.skl_latency;
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else
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latencies = dev_priv->display.wm.pri_latency;
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return wm_latency_write(file, ubuf, len, offp, latencies);
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}
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static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
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size_t len, loff_t *offp)
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{
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struct seq_file *m = file->private_data;
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struct drm_i915_private *dev_priv = m->private;
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u16 *latencies;
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if (DISPLAY_VER(dev_priv) >= 9)
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latencies = dev_priv->display.wm.skl_latency;
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else
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latencies = dev_priv->display.wm.spr_latency;
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return wm_latency_write(file, ubuf, len, offp, latencies);
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}
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static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
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size_t len, loff_t *offp)
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{
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struct seq_file *m = file->private_data;
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struct drm_i915_private *dev_priv = m->private;
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u16 *latencies;
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if (DISPLAY_VER(dev_priv) >= 9)
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latencies = dev_priv->display.wm.skl_latency;
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else
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latencies = dev_priv->display.wm.cur_latency;
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return wm_latency_write(file, ubuf, len, offp, latencies);
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}
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static const struct file_operations i915_pri_wm_latency_fops = {
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.owner = THIS_MODULE,
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.open = pri_wm_latency_open,
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.read = seq_read,
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||
|
|
.llseek = seq_lseek,
|
||
|
|
.release = single_release,
|
||
|
|
.write = pri_wm_latency_write
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct file_operations i915_spr_wm_latency_fops = {
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.open = spr_wm_latency_open,
|
||
|
|
.read = seq_read,
|
||
|
|
.llseek = seq_lseek,
|
||
|
|
.release = single_release,
|
||
|
|
.write = spr_wm_latency_write
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct file_operations i915_cur_wm_latency_fops = {
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.open = cur_wm_latency_open,
|
||
|
|
.read = seq_read,
|
||
|
|
.llseek = seq_lseek,
|
||
|
|
.release = single_release,
|
||
|
|
.write = cur_wm_latency_write
|
||
|
|
};
|
||
|
|
|
||
|
|
void intel_wm_debugfs_register(struct drm_i915_private *i915)
|
||
|
|
{
|
||
|
|
struct drm_minor *minor = i915->drm.primary;
|
||
|
|
|
||
|
|
debugfs_create_file("i915_pri_wm_latency", 0644, minor->debugfs_root,
|
||
|
|
i915, &i915_pri_wm_latency_fops);
|
||
|
|
|
||
|
|
debugfs_create_file("i915_spr_wm_latency", 0644, minor->debugfs_root,
|
||
|
|
i915, &i915_spr_wm_latency_fops);
|
||
|
|
|
||
|
|
debugfs_create_file("i915_cur_wm_latency", 0644, minor->debugfs_root,
|
||
|
|
i915, &i915_cur_wm_latency_fops);
|
||
|
|
|
||
|
|
skl_watermark_debugfs_register(i915);
|
||
|
|
}
|