161 lines
7.0 KiB
C
161 lines
7.0 KiB
C
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __SKL_WATERMARK_REGS_H__
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#define __SKL_WATERMARK_REGS_H__
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#include "intel_display_reg_defs.h"
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#define _PIPEA_MBUS_DBOX_CTL 0x7003C
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#define _PIPEB_MBUS_DBOX_CTL 0x7103C
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#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
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_PIPEB_MBUS_DBOX_CTL)
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#define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */
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#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)
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#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */
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#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)
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#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
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#define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
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#define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
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#define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2)
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#define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3)
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#define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
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#define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
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#define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)
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#define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x)
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#define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
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#define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
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#define MBUS_UBOX_CTL _MMIO(0x4503C)
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#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
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#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
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#define MBUS_CTL _MMIO(0x4438C)
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#define MBUS_JOIN REG_BIT(31)
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#define MBUS_HASHING_MODE_MASK REG_BIT(30)
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#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
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#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
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#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
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#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
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#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
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/* Watermark register definitions for SKL */
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#define _CUR_WM_A_0 0x70140
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#define _CUR_WM_B_0 0x71140
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#define _CUR_WM_SAGV_A 0x70158
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#define _CUR_WM_SAGV_B 0x71158
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#define _CUR_WM_SAGV_TRANS_A 0x7015C
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#define _CUR_WM_SAGV_TRANS_B 0x7115C
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#define _CUR_WM_TRANS_A 0x70168
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#define _CUR_WM_TRANS_B 0x71168
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#define _PLANE_WM_1_A_0 0x70240
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#define _PLANE_WM_1_B_0 0x71240
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#define _PLANE_WM_2_A_0 0x70340
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#define _PLANE_WM_2_B_0 0x71340
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#define _PLANE_WM_SAGV_1_A 0x70258
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#define _PLANE_WM_SAGV_1_B 0x71258
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#define _PLANE_WM_SAGV_2_A 0x70358
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#define _PLANE_WM_SAGV_2_B 0x71358
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#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
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#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
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#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
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#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
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#define _PLANE_WM_TRANS_1_A 0x70268
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#define _PLANE_WM_TRANS_1_B 0x71268
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#define _PLANE_WM_TRANS_2_A 0x70368
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#define _PLANE_WM_TRANS_2_B 0x71368
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#define PLANE_WM_EN (1 << 31)
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#define PLANE_WM_IGNORE_LINES (1 << 30)
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#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
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#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
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#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
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#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
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#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
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#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
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#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
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#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
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#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
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#define _PLANE_WM_BASE(pipe, plane) \
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_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
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#define PLANE_WM(pipe, plane, level) \
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_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
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#define _PLANE_WM_SAGV_1(pipe) \
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_PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
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#define _PLANE_WM_SAGV_2(pipe) \
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_PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
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#define PLANE_WM_SAGV(pipe, plane) \
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_MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
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#define _PLANE_WM_SAGV_TRANS_1(pipe) \
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_PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
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#define _PLANE_WM_SAGV_TRANS_2(pipe) \
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_PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
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#define PLANE_WM_SAGV_TRANS(pipe, plane) \
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_MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
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#define _PLANE_WM_TRANS_1(pipe) \
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_PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
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#define _PLANE_WM_TRANS_2(pipe) \
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_PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
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#define PLANE_WM_TRANS(pipe, plane) \
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_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
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#define _PLANE_BUF_CFG_1_B 0x7127c
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#define _PLANE_BUF_CFG_2_B 0x7137c
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#define _PLANE_BUF_CFG_1(pipe) \
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_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
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#define _PLANE_BUF_CFG_2(pipe) \
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_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
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#define PLANE_BUF_CFG(pipe, plane) \
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_MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
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#define _PLANE_NV12_BUF_CFG_1_B 0x71278
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#define _PLANE_NV12_BUF_CFG_2_B 0x71378
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#define _PLANE_NV12_BUF_CFG_1(pipe) \
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_PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
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#define _PLANE_NV12_BUF_CFG_2(pipe) \
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_PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
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#define PLANE_NV12_BUF_CFG(pipe, plane) \
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_MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
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/* SKL new cursor registers */
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#define _CUR_BUF_CFG_A 0x7017c
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#define _CUR_BUF_CFG_B 0x7117c
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#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
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/*
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* The below are numbered starting from "S1" on gen11/gen12, but starting
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* with display 13, the bspec switches to a 0-based numbering scheme
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* (although the addresses stay the same so new S0 = old S1, new S1 = old S2).
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* We'll just use the 0-based numbering here for all platforms since it's the
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* way things will be named by the hardware team going forward, plus it's more
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* consistent with how most of the rest of our registers are named.
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*/
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#define _DBUF_CTL_S0 0x45008
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#define _DBUF_CTL_S1 0x44FE8
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#define _DBUF_CTL_S2 0x44300
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#define _DBUF_CTL_S3 0x44304
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#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
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_DBUF_CTL_S0, \
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_DBUF_CTL_S1, \
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_DBUF_CTL_S2, \
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_DBUF_CTL_S3))
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#define DBUF_POWER_REQUEST REG_BIT(31)
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#define DBUF_POWER_STATE REG_BIT(30)
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#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
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#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
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#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */
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#define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
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#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)
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#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)
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#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)
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#define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
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#define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
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#define MTL_LATENCY_SAGV _MMIO(0x4578c)
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#define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)
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#endif /* __SKL_WATERMARK_REGS_H__ */
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