2023-08-30 16:31:07 +01:00
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef _INTEL_GSC_UC_H_
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#define _INTEL_GSC_UC_H_
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#include "intel_uc_fw.h"
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struct i915_vma;
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struct intel_context;
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2023-10-24 11:59:35 +01:00
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struct i915_gsc_proxy_component;
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2023-08-30 16:31:07 +01:00
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struct intel_gsc_uc {
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/* Generic uC firmware management */
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struct intel_uc_fw fw;
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/* GSC-specific additions */
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struct i915_vma *local; /* private memory for GSC usage */
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struct intel_context *ce; /* for submission to GSC FW via GSC engine */
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2023-10-24 11:59:35 +01:00
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/* for delayed load and proxy handling */
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struct workqueue_struct *wq;
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struct work_struct work;
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u32 gsc_work_actions; /* protected by gt->irq_lock */
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#define GSC_ACTION_FW_LOAD BIT(0)
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#define GSC_ACTION_SW_PROXY BIT(1)
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struct {
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struct i915_gsc_proxy_component *component;
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bool component_added;
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struct i915_vma *vma;
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void *to_gsc;
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void *to_csme;
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struct mutex mutex; /* protects the tee channel binding */
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} proxy;
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2023-08-30 16:31:07 +01:00
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};
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void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc);
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int intel_gsc_uc_init(struct intel_gsc_uc *gsc);
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void intel_gsc_uc_fini(struct intel_gsc_uc *gsc);
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void intel_gsc_uc_suspend(struct intel_gsc_uc *gsc);
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2023-10-24 11:59:35 +01:00
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void intel_gsc_uc_resume(struct intel_gsc_uc *gsc);
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void intel_gsc_uc_flush_work(struct intel_gsc_uc *gsc);
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2023-08-30 16:31:07 +01:00
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void intel_gsc_uc_load_start(struct intel_gsc_uc *gsc);
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static inline bool intel_gsc_uc_is_supported(struct intel_gsc_uc *gsc)
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{
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return intel_uc_fw_is_supported(&gsc->fw);
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}
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static inline bool intel_gsc_uc_is_wanted(struct intel_gsc_uc *gsc)
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{
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return intel_uc_fw_is_enabled(&gsc->fw);
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}
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static inline bool intel_gsc_uc_is_used(struct intel_gsc_uc *gsc)
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{
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GEM_BUG_ON(__intel_uc_fw_status(&gsc->fw) == INTEL_UC_FIRMWARE_SELECTED);
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return intel_uc_fw_is_available(&gsc->fw);
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}
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#endif
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