280 lines
9.1 KiB
C
280 lines
9.1 KiB
C
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// SPDX-License-Identifier: MIT
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/*
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* Copyright 2019 Intel Corporation.
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*/
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#include "i915_drv.h"
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#include "i915_utils.h"
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#include "intel_pch.h"
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/* Map PCH device id to PCH type, or PCH_NONE if unknown. */
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static enum intel_pch
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intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
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{
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switch (id) {
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case INTEL_PCH_IBX_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found Ibex Peak PCH\n");
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drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5);
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return PCH_IBX;
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case INTEL_PCH_CPT_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found CougarPoint PCH\n");
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drm_WARN_ON(&dev_priv->drm,
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GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv));
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return PCH_CPT;
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case INTEL_PCH_PPT_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n");
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drm_WARN_ON(&dev_priv->drm,
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GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv));
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/* PPT is CPT compatible */
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return PCH_CPT;
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case INTEL_PCH_LPT_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n");
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drm_WARN_ON(&dev_priv->drm,
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!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
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drm_WARN_ON(&dev_priv->drm,
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IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
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return PCH_LPT;
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case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found LynxPoint LP PCH\n");
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drm_WARN_ON(&dev_priv->drm,
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!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
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drm_WARN_ON(&dev_priv->drm,
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!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
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return PCH_LPT;
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case INTEL_PCH_WPT_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint PCH\n");
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drm_WARN_ON(&dev_priv->drm,
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!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
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drm_WARN_ON(&dev_priv->drm,
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IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
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/* WPT is LPT compatible */
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return PCH_LPT;
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case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint LP PCH\n");
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drm_WARN_ON(&dev_priv->drm,
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!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
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drm_WARN_ON(&dev_priv->drm,
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!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
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/* WPT is LPT compatible */
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return PCH_LPT;
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case INTEL_PCH_SPT_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint PCH\n");
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drm_WARN_ON(&dev_priv->drm,
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!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
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return PCH_SPT;
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case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n");
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drm_WARN_ON(&dev_priv->drm,
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!IS_SKYLAKE(dev_priv) &&
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!IS_KABYLAKE(dev_priv) &&
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!IS_COFFEELAKE(dev_priv) &&
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!IS_COMETLAKE(dev_priv));
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return PCH_SPT;
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case INTEL_PCH_KBP_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found Kaby Lake PCH (KBP)\n");
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drm_WARN_ON(&dev_priv->drm,
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!IS_SKYLAKE(dev_priv) &&
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!IS_KABYLAKE(dev_priv) &&
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!IS_COFFEELAKE(dev_priv) &&
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!IS_COMETLAKE(dev_priv));
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/* KBP is SPT compatible */
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return PCH_SPT;
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case INTEL_PCH_CNP_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n");
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drm_WARN_ON(&dev_priv->drm,
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!IS_COFFEELAKE(dev_priv) &&
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!IS_COMETLAKE(dev_priv));
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return PCH_CNP;
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case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm,
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"Found Cannon Lake LP PCH (CNP-LP)\n");
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drm_WARN_ON(&dev_priv->drm,
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!IS_COFFEELAKE(dev_priv) &&
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!IS_COMETLAKE(dev_priv));
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return PCH_CNP;
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case INTEL_PCH_CMP_DEVICE_ID_TYPE:
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case INTEL_PCH_CMP2_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n");
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drm_WARN_ON(&dev_priv->drm,
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!IS_COFFEELAKE(dev_priv) &&
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!IS_COMETLAKE(dev_priv) &&
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!IS_ROCKETLAKE(dev_priv));
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/* CMP is CNP compatible */
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return PCH_CNP;
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case INTEL_PCH_CMP_V_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n");
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drm_WARN_ON(&dev_priv->drm,
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!IS_COFFEELAKE(dev_priv) &&
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!IS_COMETLAKE(dev_priv));
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/* CMP-V is based on KBP, which is SPT compatible */
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return PCH_SPT;
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case INTEL_PCH_ICP_DEVICE_ID_TYPE:
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case INTEL_PCH_ICP2_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found Ice Lake PCH\n");
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drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
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return PCH_ICP;
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case INTEL_PCH_MCC_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n");
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drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
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/* MCC is TGP compatible */
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return PCH_TGP;
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case INTEL_PCH_TGP_DEVICE_ID_TYPE:
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case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n");
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drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) &&
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!IS_ROCKETLAKE(dev_priv) &&
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!IS_GEN9_BC(dev_priv));
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return PCH_TGP;
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case INTEL_PCH_JSP_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
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drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
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/* JSP is ICP compatible */
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return PCH_ICP;
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case INTEL_PCH_ADP_DEVICE_ID_TYPE:
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case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
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case INTEL_PCH_ADP3_DEVICE_ID_TYPE:
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case INTEL_PCH_ADP4_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
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drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) &&
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!IS_ALDERLAKE_P(dev_priv));
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return PCH_ADP;
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case INTEL_PCH_MTP_DEVICE_ID_TYPE:
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case INTEL_PCH_MTP2_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found Meteor Lake PCH\n");
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drm_WARN_ON(&dev_priv->drm, !IS_METEORLAKE(dev_priv));
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return PCH_MTP;
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default:
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return PCH_NONE;
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}
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}
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static bool intel_is_virt_pch(unsigned short id,
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unsigned short svendor, unsigned short sdevice)
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{
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return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
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id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
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(id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
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svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
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sdevice == PCI_SUBDEVICE_ID_QEMU));
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}
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static void
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intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
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unsigned short *pch_id, enum intel_pch *pch_type)
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{
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unsigned short id = 0;
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/*
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* In a virtualized passthrough environment we can be in a
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* setup where the ISA bridge is not able to be passed through.
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* In this case, a south bridge can be emulated and we have to
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* make an educated guess as to which PCH is really there.
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*/
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if (IS_METEORLAKE(dev_priv))
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id = INTEL_PCH_MTP_DEVICE_ID_TYPE;
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else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
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id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
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else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
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id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
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else if (IS_JSL_EHL(dev_priv))
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id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
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else if (IS_ICELAKE(dev_priv))
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id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
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else if (IS_COFFEELAKE(dev_priv) ||
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IS_COMETLAKE(dev_priv))
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id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
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else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
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id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
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else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
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id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
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else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
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else if (GRAPHICS_VER(dev_priv) == 6 || IS_IVYBRIDGE(dev_priv))
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id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
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else if (GRAPHICS_VER(dev_priv) == 5)
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id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
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if (id)
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drm_dbg_kms(&dev_priv->drm, "Assuming PCH ID %04x\n", id);
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else
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drm_dbg_kms(&dev_priv->drm, "Assuming no PCH\n");
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*pch_type = intel_pch_type(dev_priv, id);
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/* Sanity check virtual PCH id */
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if (drm_WARN_ON(&dev_priv->drm,
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id && *pch_type == PCH_NONE))
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id = 0;
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*pch_id = id;
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}
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void intel_detect_pch(struct drm_i915_private *dev_priv)
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{
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struct pci_dev *pch = NULL;
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unsigned short id;
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enum intel_pch pch_type;
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/* DG1 has south engine display on the same PCI device */
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if (IS_DG1(dev_priv)) {
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dev_priv->pch_type = PCH_DG1;
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return;
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} else if (IS_DG2(dev_priv)) {
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dev_priv->pch_type = PCH_DG2;
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return;
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}
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/*
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* The reason to probe ISA bridge instead of Dev31:Fun0 is to
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* make graphics device passthrough work easy for VMM, that only
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* need to expose ISA bridge to let driver know the real hardware
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* underneath. This is a requirement from virtualization team.
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*
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* In some virtualized environments (e.g. XEN), there is irrelevant
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* ISA bridge in the system. To work reliably, we should scan trhough
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* all the ISA bridge devices and check for the first match, instead
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* of only checking the first one.
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*/
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while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
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if (pch->vendor != PCI_VENDOR_ID_INTEL)
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continue;
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id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
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pch_type = intel_pch_type(dev_priv, id);
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if (pch_type != PCH_NONE) {
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dev_priv->pch_type = pch_type;
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dev_priv->pch_id = id;
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break;
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} else if (intel_is_virt_pch(id, pch->subsystem_vendor,
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pch->subsystem_device)) {
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intel_virt_detect_pch(dev_priv, &id, &pch_type);
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dev_priv->pch_type = pch_type;
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dev_priv->pch_id = id;
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break;
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}
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}
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/*
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* Use PCH_NOP (PCH but no South Display) for PCH platforms without
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* display.
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*/
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if (pch && !HAS_DISPLAY(dev_priv)) {
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drm_dbg_kms(&dev_priv->drm,
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"Display disabled, reverting to NOP PCH\n");
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dev_priv->pch_type = PCH_NOP;
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dev_priv->pch_id = 0;
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} else if (!pch) {
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if (i915_run_as_guest() && HAS_DISPLAY(dev_priv)) {
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intel_virt_detect_pch(dev_priv, &id, &pch_type);
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dev_priv->pch_type = pch_type;
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dev_priv->pch_id = id;
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} else {
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drm_dbg_kms(&dev_priv->drm, "No PCH found.\n");
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}
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}
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pci_dev_put(pch);
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}
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