301 lines
9.9 KiB
C
301 lines
9.9 KiB
C
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/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "head.h"
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#include "atom.h"
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#include "core.h"
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#include <nvif/pushc37b.h>
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#include <nvhw/class/clc37d.h>
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static int
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headc37d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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const int i = head->base.index;
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u8 depth;
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int ret;
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/*XXX: This is a dirty hack until OR depth handling is
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* improved later for deep colour etc.
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*/
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switch (asyh->or.depth) {
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case 6: depth = 5; break;
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case 5: depth = 4; break;
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case 2: depth = 1; break;
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case 0: depth = 4; break;
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default:
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depth = asyh->or.depth;
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WARN_ON(1);
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break;
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}
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if ((ret = PUSH_WAIT(push, 2)))
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return ret;
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PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
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NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) |
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NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) |
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NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) |
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NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, PIXEL_DEPTH, depth) |
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NVDEF(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, COLOR_SPACE_OVERRIDE, DISABLE));
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return 0;
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}
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static int
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headc37d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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const int i = head->base.index;
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int ret;
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if ((ret = PUSH_WAIT(push, 2)))
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return ret;
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PUSH_MTHD(push, NVC37D, HEAD_SET_PROCAMP(i),
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NVDEF(NVC37D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) |
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NVDEF(NVC37D, HEAD_SET_PROCAMP, CHROMA_LPF, DISABLE) |
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NVVAL(NVC37D, HEAD_SET_PROCAMP, SAT_COS, asyh->procamp.sat.cos) |
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NVVAL(NVC37D, HEAD_SET_PROCAMP, SAT_SINE, asyh->procamp.sat.sin) |
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NVDEF(NVC37D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA) |
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NVDEF(NVC37D, HEAD_SET_PROCAMP, RANGE_COMPRESSION, DISABLE) |
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NVDEF(NVC37D, HEAD_SET_PROCAMP, BLACK_LEVEL, GRAPHICS));
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return 0;
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}
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int
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headc37d_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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const int i = head->base.index;
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int ret;
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if ((ret = PUSH_WAIT(push, 2)))
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return ret;
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PUSH_MTHD(push, NVC37D, HEAD_SET_DITHER_CONTROL(i),
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NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |
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NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) |
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NVDEF(NVC37D, HEAD_SET_DITHER_CONTROL, OFFSET_ENABLE, DISABLE) |
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NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |
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NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
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return 0;
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}
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int
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headc37d_curs_clr(struct nv50_head *head)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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const int i = head->base.index;
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int ret;
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if ((ret = PUSH_WAIT(push, 4)))
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return ret;
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PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
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NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |
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NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8));
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PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), 0x00000000);
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return 0;
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}
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int
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headc37d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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const int i = head->base.index;
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int ret;
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if ((ret = PUSH_WAIT(push, 7)))
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return ret;
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PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i),
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NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
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NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
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NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
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NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
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NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) |
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NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, DE_GAMMA, NONE),
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HEAD_SET_CONTROL_CURSOR_COMPOSITION(i),
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NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, K1, 0xff) |
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NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, CURSOR_COLOR_FACTOR_SELECT,
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K1) |
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NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, VIEWPORT_COLOR_FACTOR_SELECT,
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NEG_K1_TIMES_SRC) |
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NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND));
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PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), asyh->curs.handle);
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PUSH_MTHD(push, NVC37D, HEAD_SET_OFFSET_CURSOR(i, 0), asyh->curs.offset >> 8);
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return 0;
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}
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int
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headc37d_curs_format(struct nv50_head *head, struct nv50_wndw_atom *asyw,
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struct nv50_head_atom *asyh)
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{
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asyh->curs.format = asyw->image.format;
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return 0;
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}
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static int
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headc37d_olut_clr(struct nv50_head *head)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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const int i = head->base.index;
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int ret;
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if ((ret = PUSH_WAIT(push, 2)))
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return ret;
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PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), 0x00000000);
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return 0;
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}
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static int
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headc37d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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const int i = head->base.index;
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int ret;
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if ((ret = PUSH_WAIT(push, 4)))
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return ret;
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PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT(i),
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NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, SIZE, asyh->olut.size) |
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NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, RANGE, asyh->olut.range) |
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NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, OUTPUT_MODE, asyh->olut.output_mode),
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HEAD_SET_OFFSET_OUTPUT_LUT(i), asyh->olut.offset >> 8,
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HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), asyh->olut.handle);
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return 0;
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}
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static bool
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headc37d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
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{
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if (size != 256 && size != 1024)
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return false;
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asyh->olut.size = size == 1024 ? NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025 :
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NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_257;
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asyh->olut.range = NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY;
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asyh->olut.output_mode = NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE;
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asyh->olut.load = head907d_olut_load;
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return true;
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}
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static int
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headc37d_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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struct nv50_head_mode *m = &asyh->mode;
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const int i = head->base.index;
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int ret;
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if ((ret = PUSH_WAIT(push, 15)))
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return ret;
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PUSH_MTHD(push, NVC37D, HEAD_SET_RASTER_SIZE(i),
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NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) |
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NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),
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HEAD_SET_RASTER_SYNC_END(i),
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NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) |
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NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),
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HEAD_SET_RASTER_BLANK_END(i),
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NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) |
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NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),
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HEAD_SET_RASTER_BLANK_START(i),
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NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) |
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NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks));
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//XXX:
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PUSH_NVSQ(push, NVC37D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);
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PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace);
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PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
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NVVAL(NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000));
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PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
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NVVAL(NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000));
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/*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */
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PUSH_MTHD(push, NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
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NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, CURSOR, USAGE_W256_H256) |
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NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, OUTPUT_LUT, USAGE_1025) |
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NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, UPSCALING_ALLOWED, TRUE));
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return 0;
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}
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int
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headc37d_view(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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const int i = head->base.index;
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int ret;
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if ((ret = PUSH_WAIT(push, 4)))
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return ret;
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PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_IN(i),
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NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) |
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NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH));
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PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
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NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) |
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NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH));
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return 0;
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}
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void
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headc37d_static_wndw_map(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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int i, end;
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for (i = head->base.index * 2, end = i + 2; i < end; i++)
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asyh->wndw.owned |= BIT(i);
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}
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const struct nv50_head_func
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headc37d = {
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.view = headc37d_view,
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.mode = headc37d_mode,
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.olut = headc37d_olut,
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.ilut_check = head907d_ilut_check,
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.olut_size = 1024,
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.olut_set = headc37d_olut_set,
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.olut_clr = headc37d_olut_clr,
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.curs_layout = head917d_curs_layout,
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.curs_format = headc37d_curs_format,
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.curs_set = headc37d_curs_set,
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.curs_clr = headc37d_curs_clr,
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.dither = headc37d_dither,
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.procamp = headc37d_procamp,
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.or = headc37d_or,
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.static_wndw_map = headc37d_static_wndw_map,
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};
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