263 lines
8.1 KiB
C
263 lines
8.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This file is part of STM32 ADC driver
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*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
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*
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*/
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#ifndef __STM32_ADC_H
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#define __STM32_ADC_H
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/*
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* STM32 - ADC global register map
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* ________________________________________________________
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* | Offset | Register |
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* --------------------------------------------------------
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* | 0x000 | Master ADC1 |
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* --------------------------------------------------------
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* | 0x100 | Slave ADC2 |
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* --------------------------------------------------------
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* | 0x200 | Slave ADC3 |
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* --------------------------------------------------------
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* | 0x300 | Master & Slave common regs |
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* --------------------------------------------------------
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*/
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/* Maximum ADC instances number per ADC block for all supported SoCs */
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#define STM32_ADC_MAX_ADCS 3
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#define STM32_ADC_OFFSET 0x100
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#define STM32_ADCX_COMN_OFFSET 0x300
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/* STM32F4 - Registers for each ADC instance */
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#define STM32F4_ADC_SR 0x00
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#define STM32F4_ADC_CR1 0x04
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#define STM32F4_ADC_CR2 0x08
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#define STM32F4_ADC_SMPR1 0x0C
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#define STM32F4_ADC_SMPR2 0x10
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#define STM32F4_ADC_HTR 0x24
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#define STM32F4_ADC_LTR 0x28
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#define STM32F4_ADC_SQR1 0x2C
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#define STM32F4_ADC_SQR2 0x30
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#define STM32F4_ADC_SQR3 0x34
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#define STM32F4_ADC_JSQR 0x38
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#define STM32F4_ADC_JDR1 0x3C
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#define STM32F4_ADC_JDR2 0x40
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#define STM32F4_ADC_JDR3 0x44
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#define STM32F4_ADC_JDR4 0x48
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#define STM32F4_ADC_DR 0x4C
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/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
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#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
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#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
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/* STM32F4_ADC_SR - bit fields */
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#define STM32F4_OVR BIT(5)
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#define STM32F4_STRT BIT(4)
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#define STM32F4_EOC BIT(1)
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/* STM32F4_ADC_CR1 - bit fields */
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#define STM32F4_OVRIE BIT(26)
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#define STM32F4_RES_SHIFT 24
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#define STM32F4_RES_MASK GENMASK(25, 24)
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#define STM32F4_SCAN BIT(8)
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#define STM32F4_EOCIE BIT(5)
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/* STM32F4_ADC_CR2 - bit fields */
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#define STM32F4_SWSTART BIT(30)
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#define STM32F4_EXTEN_SHIFT 28
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#define STM32F4_EXTEN_MASK GENMASK(29, 28)
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#define STM32F4_EXTSEL_SHIFT 24
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#define STM32F4_EXTSEL_MASK GENMASK(27, 24)
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#define STM32F4_EOCS BIT(10)
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#define STM32F4_DDS BIT(9)
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#define STM32F4_DMA BIT(8)
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#define STM32F4_ADON BIT(0)
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/* STM32F4_ADC_CSR - bit fields */
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#define STM32F4_OVR3 BIT(21)
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#define STM32F4_EOC3 BIT(17)
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#define STM32F4_OVR2 BIT(13)
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#define STM32F4_EOC2 BIT(9)
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#define STM32F4_OVR1 BIT(5)
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#define STM32F4_EOC1 BIT(1)
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/* STM32F4_ADC_CCR - bit fields */
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#define STM32F4_ADC_ADCPRE_SHIFT 16
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#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
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/* STM32H7 - Registers for each ADC instance */
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#define STM32H7_ADC_ISR 0x00
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#define STM32H7_ADC_IER 0x04
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#define STM32H7_ADC_CR 0x08
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#define STM32H7_ADC_CFGR 0x0C
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#define STM32H7_ADC_SMPR1 0x14
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#define STM32H7_ADC_SMPR2 0x18
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#define STM32H7_ADC_PCSEL 0x1C
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#define STM32H7_ADC_SQR1 0x30
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#define STM32H7_ADC_SQR2 0x34
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#define STM32H7_ADC_SQR3 0x38
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#define STM32H7_ADC_SQR4 0x3C
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#define STM32H7_ADC_DR 0x40
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#define STM32H7_ADC_DIFSEL 0xC0
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#define STM32H7_ADC_CALFACT 0xC4
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#define STM32H7_ADC_CALFACT2 0xC8
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/* STM32MP1 - ADC2 instance option register */
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#define STM32MP1_ADC2_OR 0xD0
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/* STM32MP1 - Identification registers */
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#define STM32MP1_ADC_HWCFGR0 0x3F0
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#define STM32MP1_ADC_VERR 0x3F4
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#define STM32MP1_ADC_IPDR 0x3F8
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#define STM32MP1_ADC_SIDR 0x3FC
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/* STM32MP13 - Registers for each ADC instance */
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#define STM32MP13_ADC_DIFSEL 0xB0
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#define STM32MP13_ADC_CALFACT 0xB4
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#define STM32MP13_ADC2_OR 0xC8
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/* STM32H7 - common registers for all ADC instances */
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#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
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#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
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/* STM32H7_ADC_ISR - bit fields */
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#define STM32MP1_VREGREADY BIT(12)
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#define STM32H7_OVR BIT(4)
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#define STM32H7_EOC BIT(2)
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#define STM32H7_ADRDY BIT(0)
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/* STM32H7_ADC_IER - bit fields */
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#define STM32H7_OVRIE STM32H7_OVR
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#define STM32H7_EOCIE STM32H7_EOC
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/* STM32H7_ADC_CR - bit fields */
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#define STM32H7_ADCAL BIT(31)
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#define STM32H7_ADCALDIF BIT(30)
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#define STM32H7_DEEPPWD BIT(29)
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#define STM32H7_ADVREGEN BIT(28)
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#define STM32H7_LINCALRDYW6 BIT(27)
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#define STM32H7_LINCALRDYW5 BIT(26)
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#define STM32H7_LINCALRDYW4 BIT(25)
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#define STM32H7_LINCALRDYW3 BIT(24)
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#define STM32H7_LINCALRDYW2 BIT(23)
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#define STM32H7_LINCALRDYW1 BIT(22)
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#define STM32H7_LINCALRDYW_MASK GENMASK(27, 22)
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#define STM32H7_ADCALLIN BIT(16)
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#define STM32H7_BOOST BIT(8)
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#define STM32H7_ADSTP BIT(4)
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#define STM32H7_ADSTART BIT(2)
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#define STM32H7_ADDIS BIT(1)
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#define STM32H7_ADEN BIT(0)
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/* STM32H7_ADC_CFGR bit fields */
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#define STM32H7_EXTEN_SHIFT 10
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#define STM32H7_EXTEN_MASK GENMASK(11, 10)
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#define STM32H7_EXTSEL_SHIFT 5
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#define STM32H7_EXTSEL_MASK GENMASK(9, 5)
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#define STM32H7_RES_SHIFT 2
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#define STM32H7_RES_MASK GENMASK(4, 2)
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#define STM32H7_DMNGT_SHIFT 0
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#define STM32H7_DMNGT_MASK GENMASK(1, 0)
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enum stm32h7_adc_dmngt {
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STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */
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STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */
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STM32H7_DMNGT_DFSDM, /* DFSDM mode */
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STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */
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};
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/* STM32H7_ADC_DIFSEL - bit fields */
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#define STM32H7_DIFSEL_MASK GENMASK(19, 0)
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/* STM32H7_ADC_CALFACT - bit fields */
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#define STM32H7_CALFACT_D_SHIFT 16
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#define STM32H7_CALFACT_D_MASK GENMASK(26, 16)
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#define STM32H7_CALFACT_S_SHIFT 0
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#define STM32H7_CALFACT_S_MASK GENMASK(10, 0)
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/* STM32H7_ADC_CALFACT2 - bit fields */
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#define STM32H7_LINCALFACT_SHIFT 0
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#define STM32H7_LINCALFACT_MASK GENMASK(29, 0)
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/* STM32H7_ADC_CSR - bit fields */
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#define STM32H7_OVR_SLV BIT(20)
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#define STM32H7_EOC_SLV BIT(18)
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#define STM32H7_OVR_MST BIT(4)
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#define STM32H7_EOC_MST BIT(2)
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/* STM32H7_ADC_CCR - bit fields */
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#define STM32H7_VBATEN BIT(24)
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#define STM32H7_VREFEN BIT(22)
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#define STM32H7_PRESC_SHIFT 18
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#define STM32H7_PRESC_MASK GENMASK(21, 18)
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#define STM32H7_CKMODE_SHIFT 16
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#define STM32H7_CKMODE_MASK GENMASK(17, 16)
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/* STM32MP1_ADC2_OR - bit fields */
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#define STM32MP1_VDDCOREEN BIT(0)
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/* STM32MP1_ADC_HWCFGR0 - bit fields */
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#define STM32MP1_ADCNUM_SHIFT 0
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#define STM32MP1_ADCNUM_MASK GENMASK(3, 0)
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#define STM32MP1_MULPIPE_SHIFT 4
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#define STM32MP1_MULPIPE_MASK GENMASK(7, 4)
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#define STM32MP1_OPBITS_SHIFT 8
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#define STM32MP1_OPBITS_MASK GENMASK(11, 8)
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#define STM32MP1_IDLEVALUE_SHIFT 12
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#define STM32MP1_IDLEVALUE_MASK GENMASK(15, 12)
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/* STM32MP1_ADC_VERR - bit fields */
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#define STM32MP1_MINREV_SHIFT 0
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#define STM32MP1_MINREV_MASK GENMASK(3, 0)
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#define STM32MP1_MAJREV_SHIFT 4
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#define STM32MP1_MAJREV_MASK GENMASK(7, 4)
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/* STM32MP1_ADC_IPDR - bit fields */
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#define STM32MP1_IPIDR_MASK GENMASK(31, 0)
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/* STM32MP1_ADC_SIDR - bit fields */
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#define STM32MP1_SIDR_MASK GENMASK(31, 0)
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/* STM32MP13_ADC_CFGR specific bit fields */
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#define STM32MP13_DMAEN BIT(0)
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#define STM32MP13_DMACFG BIT(1)
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#define STM32MP13_DFSDMCFG BIT(2)
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#define STM32MP13_RES_SHIFT 3
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#define STM32MP13_RES_MASK GENMASK(4, 3)
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/* STM32MP13_ADC_DIFSEL - bit fields */
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#define STM32MP13_DIFSEL_MASK GENMASK(18, 0)
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/* STM32MP13_ADC_CALFACT - bit fields */
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#define STM32MP13_CALFACT_D_SHIFT 16
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#define STM32MP13_CALFACT_D_MASK GENMASK(22, 16)
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#define STM32MP13_CALFACT_S_SHIFT 0
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#define STM32MP13_CALFACT_S_MASK GENMASK(6, 0)
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/* STM32MP13_ADC2_OR - bit fields */
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#define STM32MP13_OP2 BIT(2)
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#define STM32MP13_OP1 BIT(1)
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#define STM32MP13_OP0 BIT(0)
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#define STM32MP15_IPIDR_NUMBER 0x00110005
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#define STM32MP13_IPIDR_NUMBER 0x00110006
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/**
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* struct stm32_adc_common - stm32 ADC driver common data (for all instances)
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* @base: control registers base cpu addr
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* @phys_base: control registers base physical addr
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* @rate: clock rate used for analog circuitry
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* @vref_mv: vref voltage (mv)
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* @lock: spinlock
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*/
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struct stm32_adc_common {
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void __iomem *base;
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phys_addr_t phys_base;
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unsigned long rate;
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int vref_mv;
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spinlock_t lock; /* lock for common register */
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};
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#endif
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