2023-08-30 17:31:07 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MTK_MDP3_VPU_H__
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#define __MTK_MDP3_VPU_H__
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#include <linux/platform_device.h>
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#include "mtk-img-ipi.h"
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enum mdp_ipi_result {
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MDP_IPI_SUCCESS = 0,
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MDP_IPI_ENOMEM = 12,
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MDP_IPI_EBUSY = 16,
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MDP_IPI_EINVAL = 22,
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MDP_IPI_EMINST = 24,
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MDP_IPI_ERANGE = 34,
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MDP_IPI_NR_ERRNO,
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MDP_IPI_EOTHER = MDP_IPI_NR_ERRNO,
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MDP_IPI_PATH_CANT_MERGE,
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MDP_IPI_OP_FAIL,
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};
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struct mdp_ipi_init_msg {
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u32 status;
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u64 drv_data;
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u32 work_addr; /* [in] working buffer address */
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u32 work_size; /* [in] working buffer size */
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} __packed;
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struct mdp_ipi_deinit_msg {
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u32 status;
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u64 drv_data;
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u32 work_addr;
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} __packed;
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struct mdp_vpu_dev {
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/* synchronization protect for accessing vpu working buffer info */
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struct mutex *lock;
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struct mtk_scp *scp;
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struct completion ipi_acked;
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2023-10-24 12:59:35 +02:00
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void *param;
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dma_addr_t param_addr;
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size_t param_size;
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2023-08-30 17:31:07 +02:00
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void *work;
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dma_addr_t work_addr;
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size_t work_size;
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2023-10-24 12:59:35 +02:00
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void *config;
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dma_addr_t config_addr;
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size_t config_size;
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2023-08-30 17:31:07 +02:00
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u32 status;
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};
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void mdp_vpu_shared_mem_free(struct mdp_vpu_dev *vpu);
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int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,
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struct mutex *lock /* for sync */);
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int mdp_vpu_dev_deinit(struct mdp_vpu_dev *vpu);
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2023-10-24 12:59:35 +02:00
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int mdp_vpu_process(struct mdp_vpu_dev *vpu, struct img_ipi_frameparam *param);
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2023-08-30 17:31:07 +02:00
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#endif /* __MTK_MDP3_VPU_H__ */
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